2002 Newsgroup postings (08/29 - 09/12) Lynn Wheeler

2002 Newsgroup Postings (08/29 - 09/12)

What is microcode?
Superhot coffee
What is microcode?
why is Kerberos better than this simpler replacement
why is Kerberos better than this simpler replacement
What good is RSA when using passwords ?
Computer Architectures
What is microcode?
PDP-11 Clones was Re: Why did AMD opt for so few registers in
Moore law
What is microcode?
IEEE article on intelligence and security
IEEE article on intelligence and security
notwork
Z/OS--anything new?
Large Banking is the only chance for Mainframe
Large Banking is the only chance for Mainframe
What is microcode?
ISAs, SMP and hardware optimisations
Computer Architectures
Backdoor in AES ?
Free CPU (was: PDP-11 Clones)
Computer Architectures
Moore law
Two questions on HMACs and hashing
Do any architectures use instruction count instead of timer
Do any architectures use instruction count instead of timer
End of Moore's law and how it can influence job market
Two questions on HMACs and hashing
Do any architectures use instruction count instead of timer
Do any architectures use instruction count instead of timer
Do any architectures use instruction count instead of timer
What is microcode?
misc resource manager related folklore postings
Do any architectures use instruction count instead of timer
Cryptography
Do any architectures use instruction count instead of timer
Computer Architectures
Backdoor in AES ?
Moore law
Do any architectures use instruction count instead of timer
10 choices that were critical to the Net's success
Thirty Years Later: Lessons from the Multics Security Evaluation
another 30 year thing
Thirty Years Later: Lessons from the Multics Security Evaluation
Thirty Years Later: Lessons from the Multics Security Evaluation
10 choices that were critical to the Net's success
Do any architectures use instruction count instead of timer
10 choices that were critical to the Net's success
Do any architectures use instruction count instead of timer
IBM 2311 disk drive actuator and head assembly
Handling variable page sizes?
Itanium2 performance data from SGI
10 choices that were critical to the Net's success
10 choices that were critical to the Net's success
The problem with installable operating systems
10 choices that were critical to the Net's success
Handling variable page sizes?
Spin Loop?
Spin Loop?
Handling variable page sizes?
10 choices that were critical to the Net's success
Itanium2 performance data from SGI
10 choices that were critical to the Net's success
10 choices that were critical to the Net's success
The problem with installable operating systems
10 choices that were critical to the Net's success
The problem with installable operating systems
10 choices that were critical to the Net's success
The problem with installable operating systems
Al Gore and Fidonet [was: 10 choices]
Faster seeks (was Re: Do any architectures use instruction

What is microcode?

From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: What is microcode?
Newsgroups: comp.arch
Date: Thu, 29 Aug 2002 23:16:01 GMT

grandflashfunk@yahoo.com (Brian Nichols) writes:
Can anyone explain what microcode is? How is it different from assembly?

some discussions
https://www.garlic.com/~lynn/submain.html#360mcode 360/370 m'code

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Superhot coffee

From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Superhot coffee
Newsgroups: rec.arts.sf.science,rec.arts.sf.written,alt.folklore.computers
Date: Fri, 30 Aug 2002 13:26:38 GMT

hawk@slytherin.ds.psu.edu (Dr. Richard E. Hawkins) writes:
Thanks. I needed this badly. I've been searching for a sensible California law for my business law class, to offset all the really screwy stuff I have to explain . . .

when i first moved to mass., somebody pointed out to me that the same week cal. legislature passed a bill requiring min. 2yr degree for highway patrol, mass leg. defeated a bill requiring min. high school for highway patrol.

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

What is microcode?

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: What is microcode?
Newsgroups: comp.arch,alt.folklore.computers
Date: Fri, 30 Aug 2002 17:20:35 GMT

"Rupert Pigott" writes:
I always thought of Microcode as being a sort of "input stream decompressor" rather than an interpreter. Mind you with VAX-11 instructions you could be forgiven for treating it as an interpreter... Jeez... :)

360 & 370 were microcoded machines (few exceptions) ... i.e. there was a native processor engine and then the programming that implemented 360/370 architecture. the lower-end machines tended to be (sequential) vertical m'code (i.e. looks a lot machine/assembler) and use to run something like 10:1 (i.e. .5mip 370 engine had a 5mip microprocessor engine). Somewhat blurred distinction between 360 m'code ... and the current generation of 390 emulators running on intel architecture.

the higher end 360/370 tended to be horizontal m'code ... one m'code instruction per cycle and lots of bits controlling numerous (overlapped) functions (m'code programmer that started some operation ... like fetch ... needed to count instructions/cycles before fetch was finished and data was available). Efficiency of m'code tended to be measured in avg. cycles per instruction (since there was some amount of concurrent processing). For instance, various m'code enhancements helped reduce the avg cycle/instruction of 2.1 in the 370/165 to 1.6 in the 370/168.

random
https://www.garlic.com/~lynn/submain.html#360mcode

all the various ancillary processors in a mainframe (channels, controller, devices) were frequently various kinds of m'code programmed engines of various kinds. They could be somewhat considered embedded controllers in today's terms with really blurry distinction between calling these microcode or machine code. Some of the early 801/RISC chip efforts were targeted at the area. The 3830 disk controller was a horizontal m'code engine. The follow-on for the 3880 disk controller was jib-prime (veritical m'code) chip.

random
https://www.garlic.com/~lynn/subtopic.html#disk

when I was an undergraduate I worked on the first 360 plug-compatible controller. It started with a Interdata/3 minicomputer. A 360 channel interface board was built for the Interdata and it was programmed to emulate the 2702 terminal controller.

random
https://www.garlic.com/~lynn/submain.html#360pcm

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

why is Kerberos better than this simpler replacement

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: why is Kerberos better than this simpler replacement
Newsgroups: sci.crypt
Date: Sat, 31 Aug 2002 14:09:35 GMT

Paul Rubin <phr-n2002b@NOSPAMnightsong.com> writes:
At the time Kerberos was developed, anything using public key was tied up by patents, so they chose to stay with symmetric keys.

pk-init has been hacking(?) around in the ietf kerberos group for some time (initial kerberos authentication with public key). draft 15 had its 6month expire the end of may and i've yet to see draft 16 .. although place-holder is there:
https://web.archive.org/web/20021112170430/http://www.ietf.cnri.reston.va.us/internet-drafts/draft-ietf-cat-kerberos-pk-init-16.txt
some general ietf kerberos
https://web.archive.org/web/20030520011552/http://www.ietf.cnri.reston.va.us/ids.by.wg/krb-wg.html

general kerberos
http://web.mit.edu/kerberos/www/index.html

misc. refs:
https://www.garlic.com/~lynn/aadsm11.htm#40 ALARMED ... Only Mostly Dead ... RIP PKI ... part II
https://www.garlic.com/~lynn/aepay10.htm#33 pk-init draft (not yet a RFC)
https://www.garlic.com/~lynn/aepay10.htm#39 Microsoft Trustbridge ... Kerberos (tickets) support
https://www.garlic.com/~lynn/2002j.html#60 How to map a user account to a digital cert?

in some sense, pk-init (for kerberos) is very similar to the aads proposal i made for radius some time ago.
https://www.garlic.com/~lynn/subpubkey.html#radius

general aads
https://www.garlic.com/~lynn/x959.html#aads

from one point of view, the issue for a "from scratch" protocol ... isn't the actual bits traveling over the wire; by far the greatest effort is all the administrative infrastructure needed to maintain and support the infrastructure (which easily can be a couple orders of magnitude larger effort than the bits on the wire effort). if you don't like kerberos ... crafting some different "bits on the wire" (like aads public key) on the side of a radius implementation would leverage an existing administrative infrastructure. one of the advantages of kerberos (as well as radius) is large body of infrastructures that already have the support (again the "bits on the wire" can be totally dwarfed by the administrative infrastructure needed to support correct and timely information).

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

why is Kerberos better than this simpler replacement

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: why is Kerberos better than this simpler replacement
Newsgroups: sci.crypt
Date: Sat, 31 Aug 2002 17:32:06 GMT

Daniel James writes:
Kerberos is an attempt to solve a particular distributed access control problem without using PKI. If you remove that constraint any number of better solutions become possible.

pk-init allows for either PKI (aka CADS) or AADS type operation ... aka previous post
https://www.garlic.com/~lynn/2002l.html#3 why is kerberos better than this simpler replacement

radius is possible with password, challenge/response, and is possible to enhance for aads type operation ... with aads chip strawman
https://www.garlic.com/~lynn/x959.html#aads
https://www.garlic.com/~lynn/subpubkey.html#radius

for general radius rfc ...
https://www.garlic.com/~lynn/rfcietff.htm

and click on Term (term->RFC#) and then click on "RADIUS" in Acronym fastpath, aka:

remote authentication dial in user service (RADIUS )
see also authentication , network access server , network services
3162 2882 2869 2868 2867 2866 2865 2809 2621 2620 2619 2618 2548 2139 2138 2059 2058

general kerberos RFCs (you have to scroll for, note pk-init is still draft as per prior post, not RFC):

kerberos
see also authentication , security
3244 3129 2942 2712 2623 1964 1510 1411

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

What good is RSA when using passwords ?

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: What good is RSA when using passwords ?
Newsgroups: sci.crypt
Date: Sat, 31 Aug 2002 20:46:14 GMT

"Skybuck Flying" writes:
Using RSA solves nothing in this case, so I could just leave RSA out safe myself some possible RSA bugs and use symetric encryption like AES all the way :)

asymmetric reduces the effort in distributing verification data (aka the public key). in simple shared-secret exchange ... MITM is somewhat mitigated since they may only have to concentrate or pair-wise communication .... which nominal force some sort of out-of-band process.

note, however that some of the asymmetric solutions for out-of-band process aren't easily/possible in the shared-secret paradigm ... since the shared-secret can not only be used to verify data (decrypt) but also originate data (encrypt) .... where-as a public key is only used for verification (private key for originating isn't divulge). A public key can get published publicly in multiple places, increasing the number of different points of compromise for MITM (aka web-of-trust). Furthermore, what is being published is not a shared-secret (allowing both verification as well of origination to occur). In fact, the increase in complexity associated with PKI/CADS paradigm can bring with it a whole new set of (possibly quite obscure) vulnerabilities.

Note that PKI/CADS paradigm for asymmetric can still have a single point of compromise ... aka the specific certification authority and/or several (possibly quite complicated) business processes used by a certification authority; aka a PKI/CADS paradigm can have a large number of single point of failure .... any one being compromised can compromise the whole infrastructure (this is sometimes referred to as systemic risk).

Now there are a couple different scenarios where passwords may be used. One involves protecting access & use of the private key .... this is nominal referred to as a secret (only you know the secret ... ideally nobody else has access to it).

Note however, passwords are also used in shared-secret scenario (same character string, different semantics). Nominally asymmetric is targeted at replacing shared-secret operations .... eliminating the sharing of something that can both originate as well as verify transaction.

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Computer Architectures

From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Computer Architectures
Newsgroups: comp.arch
Date: Sat, 31 Aug 2002 21:04:28 GMT

nmm1@cus.cam.ac.uk (Nick Maclaren) writes:
The vibes from Cray are mixed. I really don't know what they are up to at all.

which cray? ... cray research? ... made those supercomputers ... got bought by SGI ... some revamping ... and then sold off to Tera?
https://web.archive.org/web/20021201102300/http://tera.com/
https://web.archive.org/web/20021224224948/http://cray.com/news/0003/acquisition.html
https://web.archive.org/web/20021224221146/http://cray.com/news/0004/acq-close.html

Seattle, Washington -- April 4, 2000 -- Tera Computer Company (Nasdaq NM: TERA), a leading designer of high-performance computer systems, announced today that it has closed its acquisition of the Cray vector supercomputer business unit, and the Cray brand name from SGI (NYSE: SGI). The definitive agreement to acquire Cray was previously announced on March 2, 2000. The acquisition was made in exchange for $15 million in cash, one million shares of unregistered common stock and a nine-month promissory note in the amount of $36.3 million subject to adjustment upon final audit.

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

What is microcode?

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: What is microcode?
Newsgroups: comp.arch,alt.folklore.computers
Date: Sun, 01 Sep 2002 14:44:03 GMT

jmfbahciv writes:
No wonder I'm terribly confused. To me, ROM implies read-only memory but I hear of BIOSes getting updated which implies a writable thingie.

BIOS ... ROM, FLASH, PROM, EEPROM, etc. ROM might be real read-only memory, PROM is programmable read-only memory i.e. you can change it ... but it may be a little harder to change than standard r/w memory.

BIOS tends to be more like system calls in ROM/PROM than 360/370 microcode. as been mentioned by others ... 360 m'code could be in something that looked like punch cards made of mylar (could be programmed manually). Customers rarely got involved in writing m'code, the wrote stuff for the 360.

number of the 370 (processor, controllers, devices) started out with the original floppy disks for "microcode" which would automatically load at power-on. processors like 370/145 had standard room for m'code but it could overflow into the "top" of processor memory. any m'code overflow would reset the standard processor addressable memory to account for that taken up by m'code.

3081 got even more complex ... it had a uc.5 microprocessor (used in 37xx controllers and the 8100 computer) as a "service processor" and a piccolo (60?mbyte) hard drive. The uc.5 would boot at power-on and read everything for the 3081 m'code from the piccolo. Functions like boot/IPL were transactions with the code running on the uc.5 service processor. M'code went into fixed amount of storage ... in some cases references were made to m'code that wasn't currently loaded (typically very low usage) and the uc.5 would "page" it. As you can imagine, having to page m'code could slow things down a bit.

The 3090 had a pair of "370s" as service processors (actually pair of 4361s) running a customized version of vm/370 release 6. The 4361s would boot VM/370 and bring up the various service processor functions and load whatever stuff was needed into the 3090. Booting the 3090 then was function of interacting with the service processor function.

random refs:
https://www.garlic.com/~lynn/submain.html#360mcode

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

PDP-11 Clones was Re: Why did AMD opt for so few registers in

From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: PDP-11 Clones was Re: Why did AMD opt for so few registers in
x86-64?
Newsgroups: comp.arch,alt.folklore.computers
Date: Sun, 01 Sep 2002 18:32:11 GMT

Eric Smith <eric-no-spam-for-me@brouhaha.com> writes:
I figured out for myself how to do this in a bitmapped display in 1977, when I was a 13 years old novice programmer. I distributed several programs that used the technique. None were published commercially, so I suppose the patent office wouldn't have accepted them as prior art.

it just has to be public ... not commercially and it can even be by you (in the case you made something public before patent application). I got caught on something by including it in a seminar at ISI/USC (not commercial). also I got the impression that if you know of pertinent material (things like prior/related art) you are suppose to include it in your patent application (or it could possibly be grounds for invalidating the patent application).

The rules are different in the US and PCT. US, you have up to a year after you have publicly divulged something to file. PCT, you can't file something after it has been divulged publicly.

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Moore law

From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Moore law
Newsgroups: comp.arch
Date: Sun, 01 Sep 2002 20:57:11 GMT

Tim Bradshaw writes:
This I mostly disagree with. I agree about hardware (thus, perhaps removing this thread's last bit of relevance to comp.arch), but I think that although it is clearly possible to write C code which is safe, it is a sufficient burden on the average programmer (and average code is written by average programmers) that they will not do that. I'm an average programmer, I suppose, and I am not at all convinced by my ability to write safe code in C. In general, high-level languages are there to make our lives easier while making the machine's life more difficult, and I think that this is one place they could make a significant difference.

my assertion is that the semantics of common C string libraries contribute significantly to C code vulnerabilities, vulnerabilities that are significantly lower occurance (one to two order magnitude) in environments with better semantics ... which is counter argument to it being (just) a hardware/software issue.

something that is fairly common across a lot of environments is dangling pointers associated with dynamic storage allocation/deallocation and in some cases, some relavance to system serialization primitives.

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

What is microcode?

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: What is microcode?
Newsgroups: comp.arch,alt.folklore.computers
Date: Mon, 02 Sep 2002 14:52:26 GMT

jmfbahciv writes:
Whenever I hear about stuff like this, the picture that immediately pops up is of the guy who has set up 10,000 dominoes and a bug drops in.

in fact that is sort of the reason it was done. Field Engineering had a requirement that they could do "bootstrap" diagnostic in the field, starting with a scope on the simplest part and going to more and more complex components. TCMs used in later processors were no longer scope'able. So the cascade goes that the service processor was scopable and could be field diagnosed (and if necessary replaced). The service processor had all sorts of probes into all parts of the system (including the TCMs) ... and the service processor could be used to "scope"/diagnose the rest of the system. The 3090 had redundant "service processors" (4361s) ... so that even if one failed ... the other was available.

random tcm refs:
https://www.garlic.com/~lynn/2000b.html#36 How to learn assembler language for OS/390 ?
https://www.garlic.com/~lynn/2000b.html#37 How to learn assembler language for OS/390 ?
https://www.garlic.com/~lynn/2000b.html#38 How to learn assembler language for OS/390 ?
https://www.garlic.com/~lynn/2000d.html#61 "all-out" vs less aggressive designs (was: Re: 36 to 32 bit transition)
https://www.garlic.com/~lynn/2001j.html#13 Parity - why even or odd (was Re: Load Locked (was: IA64 running out of steam))
https://www.garlic.com/~lynn/2001k.html#7 hot chips and nuclear reactors
https://www.garlic.com/~lynn/2002b.html#3 Microcode? (& index searching)
https://www.garlic.com/~lynn/2002d.html#13 IBM Mainframe at home
https://www.garlic.com/~lynn/2002e.html#20 What goes into a 3090?

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

IEEE article on intelligence and security

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: IEEE article on intelligence and security
Newsgroups: sci.crypt
Date: Mon, 02 Sep 2002 15:08:56 GMT

"Harris Georgiou" writes:
This is a very critical point most people miss. The goal always is to gain access to the information using every possible way, not just crack the opponent's encryption. Instead of breaking into any PGP-like application, it's much easier to exploit the user's poor security habits (people STILL use their names and birthdays as passwords).

somewhat related ... security proportional to risk:
https://www.garlic.com/~lynn/2001h.html#61 Security Proportional To Risk

and
https://www.garlic.com/~lynn/2001j.html#5 E-commerce security????

all of the major exploits that have been in the press have had nothing to do with the cryptography.
https://www.garlic.com/~lynn/subintegrity.html#fraud

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

IEEE article on intelligence and security

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: IEEE article on intelligence and security
Newsgroups: sci.crypt
Date: Mon, 02 Sep 2002 16:28:30 GMT

Anne & Lynn Wheeler writes:
somewhat related ... security proportional to risk:

or lets erect a 4' thick bank vault door in an open space ... and convince everybody that they should ignore the fact that the space has no walls and that they should only attempt to penetrate the area by compromising the vault door.

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

notwork

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: notwork
Newsgroups: alt.folklore.computers
Date: Mon, 02 Sep 2002 20:00:45 GMT

re:
https://www.garlic.com/~lynn/2002k.html#61 arrogance metrics (Benoits)

so my wife had this meeting with the corporate CFO to discuss continued funding of hsdt
https://www.garlic.com/~lynn/subnetwork.html#hsdt

he had just come from an executive board meeting where there had been presentation by somebody from communication group about the internal network was going to shortly collapse unless they quickly converted to SNA ... and he wanted to know what she thot about the claim ...

BLAAA!!! CENSORED ... sorry

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Z/OS--anything new?

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Z/OS--anything new?
Newsgroups: alt.folklore.computers
Date: Tue, 03 Sep 2002 18:28:34 GMT

lwinson@bbs.cpcn.com (lwin) writes:
For a lot of us, the "IBM mainframe operating system" means to code DISP=(NEW,CATLG,DELETE), and looking at the condition code at the end of a job's run. We don't get that involved with the stuff behind the scenes.

In the old days, when CPU time, core memory, and DASD memory were scarce we were a lot more conscious of the hardware environment since we had to allow for big critical jobs taking up the whole machine, and requesting and allocating resources that we needed for a particular job. Some years ago, "silos" with tape carts replaced reels of tape and requesting a pull from the tape library. Massive volumes of cheap DASD eliminated the need to put a lot of stuff on tape/cart altogether.

So today, a lot of things we had to do in the past have been eliminated. Along with that, gone is knowing what kind of CPU and peripherals are running since there is no need to. Further, in large organizations, those things are often changing--multiple CPUs being brought together or split up again, upgrades in DASD and CPUs, etc.

Unless one makes an conscious effort to keep up, most people wouldn't know of these changes. Further, changes such as this usually affect the systems programmers the most, with relatively little affecting application programmers.

i've asserted that before PCs there was possibly as much or more online systems that were ibm mainframe based as any other online system out there ... but because people were so pre-occupied with the DISP= varietry ... that online/time-sharing system from other vendors got a lot more notice aka lots of people may identity some other vendor with the concept of online & time-sharing .... even tho there may have been significant more of the ibm variety; it was just that the DISP= variety of ibm mainframe so dwarfed the online/time-sharing variety (except possibly for internal ibm network, development, business).

in the early '80s there was a lot of attention that there were a variety/number of different ibm mainframe kernels each with unique low-level hardware & device support ... and there was essentially totally replicated costs for each one. There was a project to look at doing a common kernel that would eliminate the replicated costs. For some purely accidental reasons ... the project got referred to as "ZM" (this is almost 20 years ago).

some of the stuff leading up to "ZM" was programming technology, hardware assurance, etc.
https://www.garlic.com/~lynn/96.html#4a John Hartmann's Birthday Party
https://www.garlic.com/~lynn/2001l.html#25 mainframe question
https://www.garlic.com/~lynn/2001m.html#53 TSS/360
https://www.garlic.com/~lynn/2001n.html#46 Blinking lights

note that part of started in the fort knox period where 801 processors were going to become the common microcode engine across the corporation
https://www.garlic.com/~lynn/2000d.html#60 "all-out" vs less aggressive designs (was: Re: 36 to 32 bit transition)
https://www.garlic.com/~lynn/2001f.html#43 Golden Era of Compilers
https://www.garlic.com/~lynn/2001h.html#69 Very CISC Instuctions (Was: why the machine word size ...)
https://www.garlic.com/~lynn/2002g.html#39 "Soul of a New Machine" Computer?
https://www.garlic.com/~lynn/2002g.html#70 Pipelining in the past
https://www.garlic.com/~lynn/2002h.html#19 PowerPC Mainframe?
https://www.garlic.com/~lynn/2002h.html#63 Sizing the application
https://www.garlic.com/~lynn/2002i.html#81 McKinley Cometh
https://www.garlic.com/~lynn/2002j.html#20 MVS on Power (was Re: McKinley Cometh...)
https://www.garlic.com/~lynn/99.html#136a checks (was S/390 on PowerPC?)

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Large Banking is the only chance for Mainframe

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Large Banking is the only chance for Mainframe
Newsgroups: bit.listserv.ibm-main
Date: Tue, 03 Sep 2002 16:07:20 GMT

"Howard Brazee" writes:
Why should mainframes be limited to batch processing? Why do banks use more batch processing than everybody else?

We are getting bigger and bigger databases - shouldn't these databases be most efficiently run on systems that fit them? We are recognizing new security and privacy needs. Our needs for large amounts of processing are different than they used to be - but they aren't smaller, they are bigger.

Sure, if the "database" consists of web pages that don't absolutely have to be co�rdinated. But lots of our needs have real-time processing that have to handle lots of data in a big hurry - with security and privacy checks. That implies a need for centralized power. What are the alternatives that can grow into appropriate solutions?

there are some trade-offs between mission/business critical and single-points-of-failure .... including truely (single-point-of-failure) centralized power. some issue between true batch and online has to do with availability and real-time constraints. we coined the term geographic survivability in the late '80s when starting ha/cmp (to distinguish from disaster/recovery which had less real-time constraints in various types of batch scenarios).

the are other costs/drivers for high availability ... like service costs (somewhat driving huge increase in mtbf for COTS hardware drives).

misc. ha/cmp
https://www.garlic.com/~lynn/subtopic.html#hacmp

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Large Banking is the only chance for Mainframe

Refed: **, - **, - **

From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Large Banking is the only chance for Mainframe
Newsgroups: bit.listserv.ibm-main
Date: Tue, 03 Sep 2002 18:44:23 GMT

IBM-MAIN@ISHAM-RESEARCH.COM (Phil Payne) writes:
I used to regard OS2 as 'MVS on the desktop'. It was pretty well impossible to get into a situation in which you couldn't collect debugging information, you could set it to reipl itself if the 'kernel' crashed, and the Workplace Shell was wonderful at reiniiaising itself and recovering.

I currently have a pernicious memory leak in Outlook Express that causes two to three boots a day on the Thinkpad.

Linux is starting to mature nicely. I think IBM's presence has changed a lot of attitudes. We will see.

there used to be a joke about RPS (for s/1) and then OS2 having been done by os/360 types from the hudson valley that had moved to boca. They somewhat came into their own on OS2 having a lot more resources than trying to cram it into the smaller resources of the S/1 (after start of OS2 timeframe, PCs were starting to outstrip capability of S/1). It was one of the places where EDX (for s/1) came about. Trying to cram a 512kbyte, MFT-II/MVT, 24-bit addressing system (RPS) into a 16bit, 64kbyte-128kbyte machine was something more of a challenge.

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

What is microcode?

From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: What is microcode?
Newsgroups: comp.arch,alt.folklore.computers
Date: Wed, 04 Sep 2002 06:03:11 GMT

"Foobar T. Clown" writes:
Anyway, during most of that time, a new PC has cost somewhere in the range of $500 to $2500 with the average, run-of-the-mill product being just over one grand. What you GET for that price has been pretty much following Moore's Law, but the PRICE remains the same. I guess it's a marketing thing.

keyboards, cases, fans, cables, wiring, lots of pieces in the monitors, cases, trucking costs, labor to demo, answer questions, etc ... haven't been subject to moore's law. i believe it is as much a packaging cost thing as a marketing thing. i think some have looked at packaging a motherboard inside a monitor (somewhat like mac) to get the next cost increment down. the downside is that there is some varience in consumer demand in monitors ... so consumers are paying some extra for tailorability.

i vaguely remember some discussion about calculators tending towards a fixed per key costs (i.e. in volume, calculator price were proportional to the number of keys).

random refs:
https://www.garlic.com/~lynn/2001n.html#81 a.f.c history checkup... (was What specifications will the standard year 2001 PC have?)
https://www.garlic.com/~lynn/2001n.html#82 a.f.c history checkup... (was What specifications will the standard year 2001 PC have?)

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

ISAs, SMP and hardware optimisations

From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: ISAs, SMP and hardware optimisations
Newsgroups: comp.arch
Date: Wed, 04 Sep 2002 15:17:29 GMT

nmm1@cus.cam.ac.uk (Nick Maclaren) writes:
3) A processor is required to make its cache changes visible and to detect changes in other caches only on the execution of certain sychronisation instructions (i.e. not loads and stores), and on certain very heavyweight operations (e.g. a context switch or non-trivial system call).

there was an attempt to do something like that in the mid-70s with 16 370/158s .... using compare&swap. it works much better in a paradigm that is heavily message passing and not with paradigm that is heavily dependent on pointer passing and shared memory. heavy pointer passing & common/shared memory has certain optimizations but they aggregavate the cache consistency issue (along with issues of legacy code migration based on such a paradigm) ... and also has poor fault isolation characteristics. message passing paradigm has all sorts of scale up characteristics whether or not memory or real pipes are being used for transport.

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Computer Architectures

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Computer Architectures
Newsgroups: comp.arch,alt.folklore.computers
Date: Thu, 05 Sep 2002 02:14:52 GMT

"glen herrmannsfeldt" writes:
For intel, I would look up the iAPX432.

That is the only one I can think of right now.

post from running across some old 432 books:
https://www.garlic.com/~lynn/2000f.html#48 Famous Machines and Software that didn't

quote in the above from one of the intros ... mentions S/38 ... which some have considered the refuge of many from the FS project. post regarding IBM FS ...
https://www.garlic.com/~lynn/2000f.html#16 FS - IBM Future System

the above contains some extracts/quotes from a web page that seems to be gone.

it also somewhat references that possibly some FS motivations was the PCMs (plug compatible manufactures). i had help start/launch some of the original PCM stuff:
https://www.garlic.com/~lynn/submain.html#360pcm

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Backdoor in AES ?

Refed: **, - **

From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Backdoor in AES ?
Newsgroups: sci.crypt
Date: Thu, 05 Sep 2002 14:44:09 GMT

Edward Elliott writes:
Financial systems don't base their security entirely on DES. The strict auditing trails banks require make your attack unlikely.

i don't know of an actual breach because of DES ... but there is all sorts of other stuff like skimming:
https://www.garlic.com/~lynn/aepay10.htm#41 ATM Scams -- Whose Liabiilty Is It, Anyway?

somewhat related to going after the easiest method ... direct DES attack isn't necessarily the easiest method. somewhat similar/related in the case of SSL and internet stuff
https://www.garlic.com/~lynn/2001h.html#61 Security proportional to risk
https://www.garlic.com/~lynn/2001h.html#58 Net banking, is it safe???

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Free CPU (was: PDP-11 Clones)

From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Free CPU (was: PDP-11 Clones)
Newsgroups: comp.arch
Date: Thu, 05 Sep 2002 13:38:57 GMT

Bernd Paysan writes:
The profit margin of a chip is only half of the story. AFAIK, on a fair calculation basis that includes stock options as "wages" (which they really are), Intel doesn't make a profit. But so does Microsoft (given how much their employees make after a few years when selling their stock options, that's no surprise).

there is a joke in redmond area about some of the early m'soft people buy up all the real estate in the area very early on. the claim is that sale of homes on this real estate to m'soft employees exceeds all salaries paid ... aka m'soft is really just a complex scheme to resell lots of real estate at significant profit to lots of people.

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Computer Architectures

Refed: **, - **, - **, - **, - **, - **, - **

From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Computer Architectures
Newsgroups: comp.arch,alt.folklore.computers
Date: Fri, 06 Sep 2002 13:39:22 GMT

"del cecchi" writes:
You really ought to write down the story of FS or get someone else to do it. I would love to read it.

ref:
https://www.garlic.com/~lynn/2002l.html#19

I was on the outside looking in ... i've posted references before that i thot it was the case of the inmates in charge of the asylum and the resulting organization effects caused the pendulum to swing way over to the opposite side (let's say somewhat all sales). my wife was relatively fresh out of umich eng grad school and worked for the guy that "owned" FS I/O at the time (somewhat aside, he had worked on cp/40 earlier) ... and she thot it was the greatest bluesky sandbox the world ever invented.

i do remember being told that it was foolish not to want to work on it .. it would probably hurt my career (also telling them that what I had running for resource management was better than what they were designing probably didn't help either).

misc. fs refs:
https://www.garlic.com/~lynn/96.html#24 old manuals
https://www.garlic.com/~lynn/99.html#100 Why won't the AS/400 die? Or, It's 1999 why do I have to learn how to use
https://www.garlic.com/~lynn/2001f.html#30 IBM's "VM for the PC" c.1984??

misc. resource manager:
https://www.garlic.com/~lynn/2002k.html#13 Difference between Unix and Linux?
https://www.garlic.com/~lynn/2002k.html#40 hung/zombie users
https://www.garlic.com/~lynn/2002k.html#46 OT (sort-of) - Does it take math skills to do data processing ?
https://www.garlic.com/~lynn/2002k.html#63 OT (sort-of) - Does it take math skills to do data processing ?
https://www.garlic.com/~lynn/2002k.html#66 OT (sort-of) - Does it take math skills to do data processing ?

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Moore law

From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Moore law
Newsgroups: comp.arch
Date: Fri, 06 Sep 2002 13:56:23 GMT

"glen herrmannsfeldt" writes:
Yes. Note that it is the (common) implementation and not the language that causes this. It is legal in C to do bounds checking even on dynamically allocated memory, but it is rarely done.

If I ever get to writing a C compiler that generates JVM code I will be able to test this better. JVM requires bounds checking on array access.

in some environments ... explicit lengths are implemented on buffers and strings which can be either handled automagically by run-time ... or the length semantics exposed. in the case of explicitly exposed length semantics, there is some reduction in vulnerabilities just because the programmer is reminded to think about length issues.

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Two questions on HMACs and hashing

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Two questions on HMACs and hashing
Newsgroups: sci.crypt
Date: Fri, 06 Sep 2002 15:30:28 GMT

Kent Briggs writes:
A digital signature is signed with a private key and authenticated by anyone with the corresponding public key. A MAC (keyed hash) is signed and authenticated with a single private key.

let's say digital signature is with a secret, private key ... and a keyed hash is secret key.

the label digital signature is more referring to a business process ... rather than technology .... the business process of keeping one part of a asymmetric key-pair really "private" ... in order to approximate the characteristics of a physical, manual signature (aka the use of signature in the term "digital signature").

However, there is more to making an approximation to a physical, manual signature (than just keeping one of the keys private). typically, a real, physical, manual signature carries with it the attribute that the person really intended to sign what they signed.

It is much easier to automate the application of "digital signatures" where there is no direct human "intention" involved. As a result some of the uses of asymmetric key technology has depreciated (or corrupted) the technology from a business sense of "signature".

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Do any architectures use instruction count instead of timer

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Do any architectures use instruction count instead of timer
 interrupts  for context changes?
Newsgroups: comp.arch,alt.folklore.computers
Date: Fri, 06 Sep 2002 16:52:43 GMT

Christopher Brian Colohan <colohan+@cs.cmu.edu> writes:
A similarly motivated, but not quite as harsh solution is being explored by the OS research community: I believe both Psycho and K42 have the concept of "hard" and "soft" preemption. The idea is this: if a user process cooperatively yields the processor, it can do so more efficiently, since it may know something about it's cache state or register usage which would allow it to yield at a convenient time.

So when the OS wants a process to yield, instead of taking the CPU away from the process, it sends it a signal requesting a "soft" preemption. The process then is allowed to stall for a short time before actually yielding the CPU. If the process waits too long before preempting, the OS will "hard" preempt it, which is slightly less efficient (since it involves a complete state save) but can not be delayed by the process.

There are all sorts of intersting issues as to how to make a fair scheduler given this scheme (ie, how do you properly deal with the process that keeps on saying "just a little bit more time!").

You can find at some information on this if you read the scheduling white paper on http://researchweb.watson.ibm.com/K42/.

CP/67 and VM/370 always had both i/o interrupt pre-emption and timer interrupt pre-emption. doing some early work on resource manager on early 370 cache machines (158s & 168s) noticed big penalty on cache hits in i/o intensive environments. as a study, the dynamic adaption stuff was enhanced to turn off i/o interrupts when application processes were running when the i/o interrupt rate exceed some threshold.

turns out this was in conjunction with some other kernel code. nominally most of the cp kernel ran disabled for all interrupts, but I noticed that a large number of I/O interrupts occurred immediately on dispatching an application process (enabled for interrupts). So i stuck an "interrupt" (enable/disable) window in the dispatcher before it went to all the trouble of actually selecting/marshaling a process for execution.

the dynamic adaptive code then controlled both the "interrupt" window and whether or not applications/processes were executing with i/o interrupts enabled.

something similar was seen with some of the early work on 370 "attached processors" ... aka two processor shared memory system ... but only one processor had physical I/O capability. some slight of hand with early SMP support and how the two processors serialized each other and handed off work to the appropriate physical processor ... had some interesting results. with hardware monitors tracking number of instructions executed ... the processor w/o i/o capability had nearly 50 percent higher MIP rate (and higher cache hit ratio) than the processor with i/o capability (also lower cache hit ratio).

of course we are talking about a time when caches were in the 8k to 64kbyte range. also the resource manager attempted to adapt the time-slice to the instruction rate.

random refs:
https://www.garlic.com/~lynn/subtopic.html#smp
https://www.garlic.com/~lynn/subtopic.html#fairshare
https://www.garlic.com/~lynn/subtopic.html#hone

earlier work that i did on cp/67 as undergraduate was playing games with the amount of work needed to resume the pre-empted task ... much of the state was saved at interrupt time ... but some could be delayed until it was decided whether or not a process was going to be resumed. If it turned out that the pre-empted task was being resumed ... I then did this stuff I called "fastpath" (i used fastpath for other stuff ... but this is where I started) .... which recognized that much of the stuff for a resumed pre-empted process didn't have to be reconstructed from scratch (could vary from 50-90 percent reduction in kernel overhead).

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Do any architectures use instruction count instead of timer

Refed: **, - **, - **

From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Do any architectures use instruction count instead of timer
 interrupts for context changes?
Newsgroups: comp.arch,alt.folklore.computers
Date: Fri, 06 Sep 2002 19:31:07 GMT

gavin@allegro.com (Gavin Scott) writes:
Sounds to me as though you want more control over where the time slices occur, such as having a system call that says "ok, I'd like not to be interrupted for the next little while and in exchange I'm willing to pay a longer time slice in the future", or simply having something like a yeild() function that says "only give me back the CPU when you can guarantee I can have the CPU for N microseconds" or something like that.

While you probably can't do much about external interrupts, it would be interesting to see what having this kind of a yeild() function would let you do.

note that time-slices have frequently been associated with resource management. resource management tends to be in terms of wall clock time ... programs executing more efficient instructions with higher cache hit ratio shouldn't be penalized compared to programs that have large proportion of multi-cycle instructions and/or very poor cache utilization characteristics. invariably if you tried to bias in favor some factor that might have huge resource use variability (possibly instructions) ... there would invariably be a pathelogical case either intentionally or non-intentionally where the operational characteristics of the system suffered. Some cases, people were spending as much time progrmaming to vagaries in the resource manager as they are programming to accomplish the application task.

the opposing trade-off is to avoid pathelogical negative feedback that because something has lousy instruction/cycle characteristics because of high cache miss characteristics ... that possibility of "early" pre-emption further aggravates cache misses.

resource management can encourage better programming practices (better cache hit ratios, more thruput per unit time, etc) but don't penalize applications for bad operating system implementation.

one of the things the resource manager offered was standard resource consumption use (wall-clock) by administrative controls (fair share, non-share share, etc) ... but could offer less frequent and longer running (the rate remained about the same ... but the granularity changed).

random
https://www.garlic.com/~lynn/subtopic.html#fairshare

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

End of Moore's law and how it can influence job market

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: End of Moore's law and how it can influence job market .....
Newsgroups: comp.arch
Date: Fri, 06 Sep 2002 19:54:57 GMT

"Rupert Pigott" writes:
Sounds pretty similar to Transputers... AFAIK IBM could even use the Transputer Trademark if they wished... I don't know enough of the details of BlueGene to really comment on the specifics though, I should dig for info. It sounds like my kind of Transputer, 4Kb never seemed enough, but 4MB seems much more useful. :)

I would kill to work on that project, even as the Janitor. :)

i actually tried to get something going with blue iliad (first 32bit 801) ... that never really got off the ground. i was looking at surface mount stuff ... but the only place in the US at the time was TI that was cutting the leads off flush. to get real (both chips and fabrication machines) surface mount you had to go to the far east. the other obvious (significant) problem was heat. one issue of surface mount was populating both sides of the board ... but blue iliad was so hot that it wasn't practical to put anything on the other side of the board. i was advocating intermixing ROMAN & ILIAD boards densely packed in cabinet which also had heat issues (roman was early cmos 370 chip ... about 3mips(?) at the time; not the hacked 68k found in pc370/washington at 100kips or the 350kips of 7437/a74). The was some discussion about being able to provide large amount of application system mips at about 1/10th the current going cost of 370 mips.

ref to some related system work
https://www.garlic.com/~lynn/96.html#4a

a later effort:
https://www.garlic.com/~lynn/95.html#13

random blue iliad:
https://www.garlic.com/~lynn/98.html#25 Merced & compilers (was Re: Effect of speed ... )
https://www.garlic.com/~lynn/99.html#66 System/1 ?
https://www.garlic.com/~lynn/2000.html#16 Computer of the century
https://www.garlic.com/~lynn/2000d.html#60 "all-out" vs less aggressive designs (was: Re: 36 to 32 bit transition)
https://www.garlic.com/~lynn/2002g.html#39 "Soul of a New Machine" Computer?
https://www.garlic.com/~lynn/2002g.html#55 Multics hardware (was Re: "Soul of a New Machine" Computer?)

random pc370/a74 refs:
https://www.garlic.com/~lynn/2000e.html#55 Why not an IBM zSeries workstation?
https://www.garlic.com/~lynn/2000e.html#56 Why not an IBM zSeries workstation?
https://www.garlic.com/~lynn/2001i.html#19 Very CISC Instuctions (Was: why the machine word size ...)
https://www.garlic.com/~lynn/2001i.html#51 DARPA was: Short Watson Biography
https://www.garlic.com/~lynn/2002d.html#4 IBM Mainframe at home

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Two questions on HMACs and hashing

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Two questions on HMACs and hashing
Newsgroups: sci.crypt
Date: Fri, 06 Sep 2002 20:12:20 GMT

Michael Sierchio writes:
In the case of a MAC, a third party can't verify a message. That's the other interesting attribute of digital signatures -- a non-participant can verify a signature.

or slightly more general; lots of parties can verify a message but only one party can have generated a specific digital signature ... origin is slightly more deterministic (assuming that business processes regarding keeping the private key secret have been observed ... note that is still not sufficient for establishing "signature" in the legal sense; possible to prove where the message/signature originated ... but not necessarily that there was intention with regard to the signature).

hmac rather than being secret private key(s) is shared-secret key(s). infrastructure impacts of single points of compromise can be mitigated if large scale distribution of shared-secret keys can be avoided aka systemic failures,

as an aside the typical PKI CADS paradigm associated with asymmetric keys has its own systemic failure modes ... sales pitch for AADS paradigm mitigating systemic failure modes:
https://www.garlic.com/~lynn/x959.html#aads

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Do any architectures use instruction count instead of timer

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Do any architectures use instruction count instead of timer
interrupts  for context changes?
Newsgroups: comp.arch,alt.folklore.computers
Date: Sat, 07 Sep 2002 14:35:20 GMT

robertwessel2@yahoo.com (Robert Wessel) writes:
Multiprocessor XA (and later) machines and MVS go out of their way to do something similar. MVS usually runs only one processor enabled for I/O interrupts. Further, many I/O "interrupts" (at least on a busy machine) are handled without actually taking a real interrupt. They get polled for with the Test-Pending-Interrupt instruction at the tail of the I/O interrupt handler, and one or two other places.

ref:
https://www.garlic.com/~lynn/2002l.html#25 Do any architectures use instruction count instead of timer

a non-processor related part of studying i/o was getting the resource manager to dynamically adapt to the "bottleneck" ... over a 10-15 year period system major bottlenecks shifted from being memory or processor constrained to be disk constrained. this resulted in my initially claiming that over a 10 year period that disks showed a significant decline in relative system thruput ... and then later claiming over a 15 year period the decline in disk relative system performance declined by an 5-10 times (aka processor and memory increased by nearly a factor of 50 but disks only increased by possibly a factor of ten ... so there was a relative decline in disk relative system thruput). the disk division got really upset by this statement ... and got the division's system performance group to refute the claim. their eventual report was that i had actually slightly understated the decline (it was actually somewhat worse).

that was eventually turned into a presentation given at guide/share regarding considerations involved in tuning disk i/o infrastructure (note in extracts in the following, DASD is acronym for "direct access storage device", aka disks):
https://www.garlic.com/~lynn/2001l.html#40 MVS History (all parts)

why back in the dark ages when i was an undergraduate ... i had redone the os/360 mft&mvt sysgens so that the order of system file copying to new disk(s) ordered them so as to optimize arm seek distances (which got nearly 3-fold improvement in the majority of the university's workload).
https://www.garlic.com/~lynn/94.html#18 CP/67 & OS MFT14
https://www.garlic.com/~lynn/94.html#20 CP/67 & OS MFT14
https://www.garlic.com/~lynn/97.html#22 Pre S/360 IBM Operating Systems?
https://www.garlic.com/~lynn/97.html#28 IA64 Self Virtualizable?
https://www.garlic.com/~lynn/98.html#21 Reviving the OS/360 thread (Questions about OS/360)
https://www.garlic.com/~lynn/99.html#93 MVS vs HASP vs JES (was 2821)
https://www.garlic.com/~lynn/99.html#174 S/360 history
https://www.garlic.com/~lynn/2000c.html#10 IBM 1460
https://www.garlic.com/~lynn/2000d.html#50 Navy orders supercomputer
https://www.garlic.com/~lynn/2001.html#26 Disk caching and file systems. Disk history...people forget
https://www.garlic.com/~lynn/2001f.html#26 Price of core memory
https://www.garlic.com/~lynn/2001h.html#12 checking some myths.
https://www.garlic.com/~lynn/2001k.html#37 Is anybody out there still writting BAL 370.
https://www.garlic.com/~lynn/2001l.html#39 is this correct ? OS/360 became MVS and MVS >> OS/390
https://www.garlic.com/~lynn/2002c.html#45 cp/67 addenda (cross-post warning)

I then did a rewrite of the cp/67 arm queuing code from fifo to a simple elevator type algorithm that would nearly double disk arm access rate under heavy load.

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Do any architectures use instruction count instead of timer

From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Do any architectures use instruction count instead of timer
interrupts  for context changes?
Newsgroups: comp.arch,alt.folklore.computers
Date: Sat, 07 Sep 2002 14:42:44 GMT

Anne & Lynn Wheeler writes:
that was eventually turned into a presentation given at guide/share regarding considerations involved in tuning disk i/o infrastructure (note in extracts in the following, DASD is acronym for "direct access storage device", aka disks):
https://www.garlic.com/~lynn/2001l.html#40 MVS History (all parts)

oops, finger slip that particular references is:
https://www.garlic.com/~lynn/2001l.html#46 MVS History (all parts)

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Do any architectures use instruction count instead of timer

From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Do any architectures use instruction count instead of timer
 interrupts  for context changes?
Newsgroups: alt.folklore.computers
Date: Sat, 07 Sep 2002 15:17:53 GMT

and just a.f.c. posting from year ago ... a 20 year old survey of computers at CMU, Bell Labs, LBL, Stanford & MIT:
https://www.garlic.com/~lynn/2001l.html#61 MVS History (all parts)

number of 750 & 780s but some number of altos & pergs (& 26 lisp machines at mit)

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

What is microcode?

From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: What is microcode?
Newsgroups: alt.folklore.computers
Date: Sat, 07 Sep 2002 16:37:01 GMT

jmfbahciv writes:
Bunny suits? [emoticon looks at poster with a puzzled look thinking, "The biz really has gone nuts."]

i had to do a couple hours in bunny suit this summer .... i don't envy the people that have to do it day-in, day-out, one of the other issues mentioned was the shoulder fatique from the constant air downflow, ... the pressure isn't significant but effect builds up after awhile.

they've done a lot of work avoiding having to go the next step ... suits that are totally sealed (and their own air supply) .. part of it is the constant downward air flow.

random ref:
https://www.garlic.com/~lynn/2002j.html#71 history of CMS

a few years ago, my youngest had a summer job on construction crew building a chip fabrication "clean room" building (in austin, i forget which one). the outer shell went up and then was "cleaned" ... and then workers had to observe clean room construction procedures (not quite bunny suits).

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

misc resource manager related folklore postings

Date: Sat, 07 Sep 2002 10:13:20 -0600
Newsgroups: bit.listserv.vmesa-l
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: misc resource manager related folklore postings

misc. recent resource manager folklore postings (some x-post with ibm-main)

https://www.garlic.com/~lynn/2002k.html#13 Difference between Unix and Linux?
https://www.garlic.com/~lynn/2002k.html#40 hung/zombie users
https://www.garlic.com/~lynn/2002k.html#46 OT (sort-of) - Does it take math skills to do data processing ?
https://www.garlic.com/~lynn/2002k.html#63 OT (sort-of) - Does it take math skills to do data processing ?
https://www.garlic.com/~lynn/2002k.html#66 OT (sort-of) - Does it take math skills to do data processing ?
https://www.garlic.com/~lynn/2002l.html#22 Computer Architectures
https://www.garlic.com/~lynn/2002l.html#25 Do any architectures use instruction count instead of timer
https://www.garlic.com/~lynn/2002l.html#26 Do any architectures use instruction count instead of timer

Do any architectures use instruction count instead of timer

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Do any architectures use instruction count instead of timer
 interrupts  for context changes?
Newsgroups: comp.arch,alt.folklore.computers
Date: Sat, 07 Sep 2002 22:47:38 GMT

Anne & Lynn Wheeler writes:
a non-processor related part of studying i/o was getting the resource manager to dynamically adapt to the "bottleneck" ... over a 10-15 year period system major bottlenecks shifted from being memory or processor constrained to be disk constrained. this resulted in my initially claiming that over a 10 year period that disks showed a significant decline in relative system thruput ... and then later claiming over a 15 year period the decline in disk relative system performance declined by an 5-10 times (aka processor and memory increased by nearly a factor of 50 but disks only increased by possibly a factor of ten ... so there was a relative decline in disk relative system thruput). the disk division got really upset by this statement ... and got the division's system performance group to refute the claim. their eventual report was that i had actually slightly understated the decline (it was actually somewhat worse).

the other part of the claim was that in going from cp/67 to vm/hpo 10-15 years later ... if it was a processor issue, the number of active users should have increased from 80 to 4000 (an increase of fifty times). since the number of users typically was on the order of 320 (an increase of only four times), there were obviously other factors in play.

configuration comparison with some ref to CMU, Bell Labs, LBL, Stanford and MIT
https://www.garlic.com/~lynn/2001l.html#61 MVS History (all parts)

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Cryptography

Refed: **, - **, - **

From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Cryptography
Newsgroups: alt.computer.security
Date: Sun, 08 Sep 2002 13:04:41 GMT

"Spelcher" <nope> writes:
I like most everyday people have shrouded a large cloud of mystery around encryption etc.. then I got to wondering, what if I created a COM object that took a credit card #, diced it up into for parts, converted to HEX, times it by a random number, divided it by the amount of seconds until the year 3000 blah blah blah... kept all necesary puzzle pieces in random places in a database.. ? Is this is a basic form of cryptography? How could this be considered unsafe? I can hardly imagine someone going through the trouble of cracking it, besides the fact that you'd have no access to the hashes created.

another form of cryptography is to create a standard where every transaction is digitally signed:
https://www.garlic.com/~lynn/x959.html#x959

then having a business process where the account number can only be used in an authenticated (signed) transaction eliminates the account number as a point of attack (i.e. shared-secret).

the current situation is that account number is essentially a shared-secret but has to be accessed by lots of different business processes by numerous parties ... meaning that it has to be in the clear:
https://www.garlic.com/~lynn/aadsm6.htm#websecure merchant web server security
https://www.garlic.com/~lynn/aepay7.htm#netbank2 net banking, is it safe?? ... security proportional to risk
https://www.garlic.com/~lynn/aepay7.htm#netsecure some recent threads on netbanking & e-commerce security
https://www.garlic.com/~lynn/aadsm10.htm#cfppki13 CFP: PKI research workshop
https://www.garlic.com/~lynn/aepay10.htm#20 Security Proportional to Risk (was: IBM Mainframe at home)

the problem is that with all the business processes accessing the number ... that either it has to be stored in the clear in the database ... or every business process needs the ability to decrypt the data (as per above ... security proportional to risk threads). If it is obfuscated/encrypted in the database ... then each of the business processes becomes a target because each one needs to have the secret to decrypt the numbers (aka an attack is to copy the whole database and all the apps) . somewhat related:
https://www.garlic.com/~lynn/2001j.html#5 E-commerce security????
https://www.garlic.com/~lynn/2001j.html#54 Does "Strong Security" Mean Anything?

more general threads:
https://www.garlic.com/~lynn/subintegrity.html#fraud

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Do any architectures use instruction count instead of timer

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Do any architectures use instruction count instead of timer
interrupts  for context changes?
Newsgroups: comp.arch,alt.folklore.computers
Date: Mon, 09 Sep 2002 14:27:26 GMT

nmm1@cus.cam.ac.uk (Nick Maclaren) writes:
No, no, that is the approach I have been railing against for years!

What you do is to design a slightly higher-level, more abstract interface with built-in asynchronicity, zero-copy and explicit committal semantics. The system-dependent optimisations can then be done by the driver without reference to the application.

some of the page-mapped stuff have been able to do that ... although the unix paradigms have been heavy buffer copy. the straight one-level store implementations started out not having any management semantics once the mapping operation was performed ... just treated stuff as simple synchronous page faults. this is one of the places that TSS360/370 got into trouble. i had done one for cms in the early '70s that preserved some of the filesystem semantic hints that helped with asynchronicity & zero copy:
https://www.garlic.com/~lynn/submain.html#mmap

the previous reference to journal file system ... there is journalling of metadata ... and there are log-structured filesystems. the work by the bsd fast file system on log-structured filesystem seemed to indicate that the advantage of writing at the current arm location was offset by the periodic garbage collection. The is somewhat independent of the contiguous allocation stuff that as been traditionally part of the OS/360 (and current descendants) since the '60s (initial allocation and extents ... potentially multi-cylinder initial allocation and then extents in either tracks or cylinders).

the one place that log structured types of writes seem to have worked is with the paging strategy for mvs & vm developed in the early '80s for big pages. disk space was allocated typically ten times larger than was going to be used. for writing out ... a full track worth of 4k pages were collected from the same address space (initially for 3380, ten pages) and written as one unit at the current arm position. Since allocation was sparce (possibly 10 percent) ... there were always nearby empty tracks to the current arm position. Immediately trailing the current head position would be full ... as the arm proceeding sequentially across the disk surface. faults for any page in a "big page" would bring all pages for the track (and make the track available). effectively explict garbage collection (as in a traditional log-structured file system) was eliminated by the transient nature of pages out on disk.

misc. big page discussions:
https://www.garlic.com/~lynn/2001k.html#60 Defrag in linux? - Newbie question
https://www.garlic.com/~lynn/2002b.html#20 index searching
https://www.garlic.com/~lynn/2002c.html#29 Page size (was: VAX, M68K complex instructions)
https://www.garlic.com/~lynn/2002c.html#48 Swapper was Re: History of Login Names
https://www.garlic.com/~lynn/2002e.html#8 What are some impressive page rates?
https://www.garlic.com/~lynn/2002e.html#11 What are some impressive page rates?
https://www.garlic.com/~lynn/2002f.html#20 Blade architectures

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Computer Architectures

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Computer Architectures
Newsgroups: comp.arch,alt.folklore.computers
Date: Mon, 09 Sep 2002 14:42:10 GMT

"Rupert Pigott" writes:
Could have fooled me, I'm still seeing MIPS processors being produced and new ones popping up ! They lost the benchmarketing war, but they're still plugging away. :)

as an aside ... the guy that my wife and i reported to when we were doing HA/CMP had been at motorola before joining the RIOS group and doing a lot work on first RIOS chipset. When somerset was formed he headed that up ... and then left to be president of MIPS. in the past there has been this joke about there only being 200 people in the industry.

random ha/cmp stuff:
https://www.garlic.com/~lynn/95.html#13
https://www.garlic.com/~lynn/subtopic.html#hacmp

random somerset refs:
https://www.garlic.com/~lynn/2000d.html#60 "all-out" vs less aggressive designs (was: Re: 36 to 32 bit transition)
https://www.garlic.com/~lynn/2001g.html#23 IA64 Rocks My World
https://www.garlic.com/~lynn/2001i.html#28 Proper ISA lifespan?
https://www.garlic.com/~lynn/2001j.html#37 Proper ISA lifespan?
https://www.garlic.com/~lynn/2002g.html#12 "Soul of a New Machine" Computer?
https://www.garlic.com/~lynn/2002g.html#14 "Soul of a New Machine" Computer?
https://www.garlic.com/~lynn/2002i.html#81 McKinley Cometh

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Backdoor in AES ?

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Backdoor in AES ?
Newsgroups: sci.crypt
Date: Mon, 09 Sep 2002 15:04:14 GMT

Bryan Olson writes:
As I understand things, triple DES was not approved until the third revision of FIPS 46. Has NIST or NSA ever approved DESX?

i believe in the past NIST would do FIPS standards from scratch. a couple years ago ... there was some NIST announcement that NIST would accept various standards as-is ... without redoing them from scratch. I believe some of this was done related to X9.62 ecdsa ... for fips186-2. also X9 did a lot of the standards work on triple-des. misc. pointers to ANSI X9 and ISO TC68:
https://www.garlic.com/~lynn/x959.html#x959

there is also a lot of joint work in biometrics going on in the area of x9.84 (between X9, NIST, and some other organizations).

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Moore law

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Moore law
Newsgroups: comp.arch
Date: Mon, 09 Sep 2002 18:53:13 GMT

Terje Mathisen writes:
a) It is almost always possible to modify the problem in such a way as to replace a hard problem with something easier.

b) The algorithm is rarely optimal.

c) You can often exchange up-front/batch processing for better real-time performance. (This is part of what I mean with my .sig)

a couple years ago ... my wife and i got brought in to look at a large database application (using conventional wisdom implementation) that if ever deployed was going to take two weeks elapsed time processing for doing end-of-day work .... and nearly two years elapsed time processing for doing end-of-month work. we got the end-of-day down to 90 minutes and end-of-month down to under 24hrs (but we had to use a lot of non-conventional wisdom approaches).

example of going from assembler to interpreted code (and making it ten times faster with introduction of new optimization):
https://www.garlic.com/~lynn/94.html#11 REXX
https://www.garlic.com/~lynn/2000b.html#32 20th March 2000
https://www.garlic.com/~lynn/2000b.html#33 20th March 2000
https://www.garlic.com/~lynn/2001c.html#0 Z/90, S/390, 370/ESA (slightly off topic)
https://www.garlic.com/~lynn/2002g.html#27 Security Issues of using Internet Banking
https://www.garlic.com/~lynn/2002h.html#37 Computers in Science Fiction
https://www.garlic.com/~lynn/2002k.html#38 GOTOs cross-posting

example of going from assembler to C ... but more than just an algorithm change .... there was a whole paradigm change in how the problem was looked at (work redoing "routes" part of large res system):
https://www.garlic.com/~lynn/96.html#29 Mainframes & Unix
https://www.garlic.com/~lynn/97.html#11 OSes commerical, history
https://www.garlic.com/~lynn/99.html#17 Old Computers
https://www.garlic.com/~lynn/99.html#100 Why won't the AS/400 die? Or, It's 1999 why do I have to learn how to use
https://www.garlic.com/~lynn/99.html#103 IBM 9020 computers used by FAA (was Re: EPO stories (was: HELP IT'S HOT!!!!!))
https://www.garlic.com/~lynn/99.html#136a checks (was S/390 on PowerPC?)
https://www.garlic.com/~lynn/2000f.html#20 Competitors to SABRE?
https://www.garlic.com/~lynn/2001.html#26 Disk caching and file systems. Disk history...people forget
https://www.garlic.com/~lynn/2001.html#62 California DMV
https://www.garlic.com/~lynn/2001d.html#69 Block oriented I/O over IP
https://www.garlic.com/~lynn/2001d.html#74 Pentium 4 Prefetch engine?
https://www.garlic.com/~lynn/2001g.html#45 Did AT&T offer Unix to Digital Equipment in the 70s?
https://www.garlic.com/~lynn/2001g.html#49 Did AT&T offer Unix to Digital Equipment in the 70s?
https://www.garlic.com/~lynn/2001h.html#76 Other oddball IBM System 360's ?
https://www.garlic.com/~lynn/2001j.html#17 I hate Compaq
https://www.garlic.com/~lynn/2001n.html#0 TSS/360
https://www.garlic.com/~lynn/2001n.html#3 News IBM loses supercomputer crown
https://www.garlic.com/~lynn/2002g.html#2 Computers in Science Fiction
https://www.garlic.com/~lynn/2002g.html#3 Why are Mainframe Computers really still in use at all?
https://www.garlic.com/~lynn/2002h.html#12 Why did OSI fail compared with TCP-IP?
https://www.garlic.com/~lynn/2002h.html#43 IBM doing anything for 50th Anniv?
https://www.garlic.com/~lynn/2002i.html#83 HONE
https://www.garlic.com/~lynn/2002j.html#83 Summary: Robots of Doom

various types of just making assembler faster ... including stuff like "fastpath" (and sometimes a paradigm change):
https://www.garlic.com/~lynn/93.html#1 360/67, was Re: IBM's Project F/S ?
https://www.garlic.com/~lynn/94.html#2 Schedulers
https://www.garlic.com/~lynn/94.html#54 How Do the Old Mainframes
https://www.garlic.com/~lynn/97.html#22 Pre S/360 IBM Operating Systems?
https://www.garlic.com/~lynn/99.html#230 Radius Help help!!!
https://www.garlic.com/~lynn/2001n.html#20 New Virus: Emails sent with no message body and _ prefixed to email address
https://www.garlic.com/~lynn/2002.html#14 index searching
https://www.garlic.com/~lynn/2002c.html#45 cp/67 addenda (cross-post warning)
https://www.garlic.com/~lynn/2002f.html#57 IBM competes with Sun w/new Chips
https://www.garlic.com/~lynn/2002g.html#32 Secure Device Drivers
https://www.garlic.com/~lynn/2002g.html#50 Why did OSI fail compared with TCP-IP?
https://www.garlic.com/~lynn/2002i.html#42 CDC6600 - just how powerful a machine was it?
https://www.garlic.com/~lynn/2002k.html#66 OT (sort-of) - Does it take math skills to do data processing ?
https://www.garlic.com/~lynn/2002l.html#4 why is Kerberos better than this simpler replacement
https://www.garlic.com/~lynn/2002l.html#25 Do any architectures use instruction count instead of timer

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Do any architectures use instruction count instead of timer

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Do any architectures use instruction count instead of timer
interrupts  for context changes?
Newsgroups: comp.arch,alt.folklore.computers
Date: Mon, 09 Sep 2002 20:16:13 GMT

"Rupert Pigott" writes:
I should have explained, each arm has 8 heads per platter... So for an 8in diameter drive you'd have a head per 0.5in (max) of platter. Someone in alt.folklore brought this idea up a few months ago, drives used to be built like this when arms didn't move. For a 14in the stats ain't quite as good. But you still get the bandwidth overkill. :)

there were two models of the 2305 fixed head disk .... both had the same number of heads ... but one had half the heads offset 180 degrees and only half as many tracks ... and had half the rotational latency.

then there was the "1655" which was an "electronic memory" simulation of a 2305 (even lower latency).

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

10 choices that were critical to the Net's success

From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: 10 choices that were critical to the Net's success
Newsgroups: alt.folklore.computers
Date: Mon, 09 Sep 2002 21:52:07 GMT

ref:
http://www.siliconvalley.com/mld/siliconvalley/business/columnists/4029770.htm?template=contentModules/printstory.jsp

some comments related to this in different mailing list:
https://www.garlic.com/~lynn/aadsm12.htm#23

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Thirty Years Later: Lessons from the Multics Security Evaluation

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Thirty Years Later: Lessons from the Multics Security Evaluation
Newsgroups: alt.folklore.computers,comp.arch
Date: Mon, 09 Sep 2002 23:08:19 GMT

some of the sections in the paper:
2.2 Security as Standard Product Feature
2.3 No Buffer Overflows
2.4 Minimizing Complexity

http://domino.watson.ibm.com/library/cyberdig.nsf/papers/FDEFBEBC9DD3E35485256C2C004B0F0D/$File/RC22534.pdf
above 404, but now can be found at
http://www.acsac.org/2002/papers/classic-multics.pdf

from the intro in the above:
This Research Report consists of two invited papers for the Classic Papers section of the 18 th Annual Computer Security Applications Conference (ACSAC) to be held 9–13 December 2002 in Las Vegas, NV. The papers will be available on the web after the conference at
http://www.acsac.org/

The first paper, Thirty Years Later: Lessons from the Multics Security Evaluation, is a commentary on the second paper, discussing the implications of the second paper's results on contemporary computer security issues. Copyright will be transferred on the first paper.

The second paper, Multics Security Evaluation: Vulnerability Analysis is a reprint of a US Air Force report, first published in 1974. It is a government document, approved for public release, distribution unlimited, and is not subject to copyright. This reprint does not include the original computer listings. They can be found at
http://csrc.nist.gov/publications/history/karg74.pdf

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

another 30 year thing

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Date: Mon, 09 Sep 2002 18:05:43 -0600
Newsgroups: bit.listserv.vmesa-l
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: another 30 year thing

note that this was in the same building (545tech sq) as cp/67 and initial VM/370 work and shared common heritage back to ctss
https://www.garlic.com/~lynn/2002l.html#42 Thirty Years Later:

other 545 tech. sq related postings:
https://www.garlic.com/~lynn/subtopic.html#545tech

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Thirty Years Later: Lessons from the Multics Security Evaluation

From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Thirty Years Later: Lessons from the Multics Security Evaluation
Newsgroups: alt.folklore.computers
Date: Tue, 10 Sep 2002 00:51:48 GMT

generic multics web site
https://www.multicians.org/

one of the sections in the mentioned paper was on pli ... multics pli:
https://www.multicians.org/pl1.html

air force data center:
https://www.multicians.org/site-afdsc.html

related reference to air force data center
https://www.garlic.com/~lynn/2001m.html#12 Multics Nostalgia
https://www.garlic.com/~lynn/2001m.html#15 departmental servers

i lived on the 4th floor of 545 tech sq. ... these guys on higher floors in the same building. misc. 545 tech sq. postings
https://www.garlic.com/~lynn/subtopic.html#545tech

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Thirty Years Later: Lessons from the Multics Security Evaluation

From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Thirty Years Later: Lessons from the Multics Security Evaluation
Newsgroups: comp.security.misc
Date: Tue, 10 Sep 2002 02:33:18 GMT

ref:
https://www.garlic.com/~lynn/2002l.html#42 Thirty Years Later: Lessons from the Multics Security Evaluation
https://www.garlic.com/~lynn/2002l.html#44 Thirty Years Later: Lessons from the Multics Security Evaluation

the above refs mention no buffer overflow/exploits

some recent buffer handling exploit discussions:
https://www.garlic.com/~lynn/2001c.html#35 How Commercial-Off-The-Shelf Systems make society vulnerable
https://www.garlic.com/~lynn/2001c.html#36 How Commercial-Off-The-Shelf Systems make society vulnerable
https://www.garlic.com/~lynn/2001n.html#76 Buffer overflow
https://www.garlic.com/~lynn/2002e.html#58 O'Reilly C Book
https://www.garlic.com/~lynn/2002l.html#9 Moore law
https://www.garlic.com/~lynn/2002l.html#23 Moore law
https://www.garlic.com/~lynn/2002l.html#36 Do any architectures use instruction count instead of timer

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

10 choices that were critical to the Net's success

From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: 10 choices that were critical to the Net's success
Newsgroups: alt.folklore.computers
Date: Tue, 10 Sep 2002 17:33:15 GMT

eugene@cse.ucsc.edu (Eugene Miya) writes:
I saw this in the Murky on Sunday. Some of these are wrong in the details.

NSF pay for BSD? Gillmor is clueless; he should not have propagated this.

choice comment on darpa funding/oversite ...
http://ezine.daemonnews.org/199909/usenix-kirk.html

previous references:
https://www.garlic.com/~lynn/2000e.html#27 OCF, PC/SC and GOP
https://www.garlic.com/~lynn/2000e.html#28 Is Al Gore The Father of the Internet?^
https://www.garlic.com/~lynn/2000e.html#29 Vint Cerf and Robert Kahn and their political opinions
https://www.garlic.com/~lynn/2002h.html#15 Coulda, Woulda, Shoudda moments?

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Do any architectures use instruction count instead of timer

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Do any architectures use instruction count instead of timer
 interrupts  for context changes?
Newsgroups: comp.arch,alt.folklore.computers
Date: Tue, 10 Sep 2002 19:08:27 GMT

hack@watson.ibm.com (hack) writes:
Please rememember that IBM is (a little bit) more than OS/360 through z/OS. Other IBM operating systems exposed conceptually cleaner interfaces. Too bad that at the device level the OS/360 view prevailed to the extent that FBA (Fixed Block Architecture, introduced in late 70s) effectively died out.

i believe i got an cost estimate from STL that even if there were given the os/360 fully developed code (i.e. stuff like multi-track searches for VTOCS & PDS) it would still cost $26m to ship FBA support as part of standard MVS release (I don't know if that was a realistic number or they just didn't want to do it).

past comments about fba support ...
https://www.garlic.com/~lynn/2001.html#54 FBA History Question (was: RE: What's the meaning of track overfl ow?)
https://www.garlic.com/~lynn/2002g.html#13 Secure Device Drivers

i believe the claim now is that everything is actually some type of FBA, at least physically ... and any CKD stuff is emulated.

also, i believe that the san jose & rochester ibm guys claim original credit for raid ... refs to original raid patent:
https://www.garlic.com/~lynn/2002e.html#4 Mainframers: Take back the light

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

10 choices that were critical to the Net's success

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: 10 choices that were critical to the Net's success
Newsgroups: alt.folklore.computers
Date: Tue, 10 Sep 2002 18:56:55 GMT

"psc_kent" writes:
It is quite likely that the Internet would have stayed a publicly-funded, government-university-research tool, in the absence of Public Law 102-194.

It is only Gore's poor choice of verbs in a 1999 TV interview (he might have chosen "commercialized", "privatized", or "deregulated"; but he said "created", often misquoted as "invented") that causes people to ignore his accomplishment.

there was already significant non-NSF (commercial and non-commercial, at least starting with the 1/1/83 switch-over to IP) stuff going on in parallel with the NSF funded stuff. In addition, the NSFNET stuff had significant commercial contributions. At the time of interop '88 there was significant commercial activity. I would contend that by 1990, it was cheaper to get the same service from commerical entities than it was to continue to operate their own "private" operation.

there continued to be funding (or at least backing) for high-speed gov. projects that were supposed to be out in front of where the industry was at any moment .... but by the early '90s there was significant market that the industry was probably starting to spend more on R&D than the gov. In fact, I believe the "federal" high-speed test bed at LLNL, vendors were asked to donate for the operation. About a year later, some far east country went to each of the vendors that took part in the high speed test bed (on their own nickel) and actually paid each one (full retail) to duplicate the setup.

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Do any architectures use instruction count instead of timer

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Do any architectures use instruction count instead of timer
interrupts  for context changes?
Newsgroups: comp.arch,alt.folklore.computers
Date: Tue, 10 Sep 2002 19:37:49 GMT

nmm1@cus.cam.ac.uk (Nick Maclaren) writes:
Introduce by IBM in an IBM mainframe context, please! It was well established elsewhere by the 1960s.

one might look at it in reverse. ibm introduced CKD in the '60s as a solution to limited memory resources. non-CKD tended to have index of where stuff was ... either in memory or having to flow thru memory. CKD allowed keys to be stored with data (in addition to reformating as to key/data recording on surface) ... and the disk/controller asked to search for the key (i.e. you didn't have to read the index into core and use computer processing time to figure out which record your data was stored at).

CP & CMS (CP/67, VM/370, carried over from CTSS) treated CKD as logical FBA from the very beginning. Both CMS & Unix (via multics) carry common heritage back to CTSS.

by at least the mid-70s the performance trade-off had shifted and typical memory sizes made it more effecient to keep the indexes around rather than having the disk scan for them. by that time the issue was probably the typical legacy problem ... like y2k or any of the other legacy issues ... how to transition all the old stuff (however the longer it is delayed, the bigger the cost when it is finally faced up to). preserving CKD paradigm was even creating some severe performance penalties by at least the late '70s. misc. multi-track search threads:
https://www.garlic.com/~lynn/93.html#29 Log Structured filesystems -- think twice
https://www.garlic.com/~lynn/94.html#35 mainframe CKD disks & PDS files (looong... warning)
https://www.garlic.com/~lynn/97.html#16 Why Mainframes?
https://www.garlic.com/~lynn/97.html#29 IA64 Self Virtualizable?
https://www.garlic.com/~lynn/99.html#75 Read if over 40 and have Mainframe background
https://www.garlic.com/~lynn/2000f.html#18 OT?
https://www.garlic.com/~lynn/2000f.html#19 OT?
https://www.garlic.com/~lynn/2000f.html#42 IBM 3340 help
https://www.garlic.com/~lynn/2000g.html#51 > 512 byte disk blocks (was: 4M pages are a bad idea)
https://www.garlic.com/~lynn/2000g.html#52 > 512 byte disk blocks (was: 4M pages are a bad idea)
https://www.garlic.com/~lynn/2001c.html#17 database (or b-tree) page sizes
https://www.garlic.com/~lynn/2001d.html#60 VTOC/VTOC INDEX/VVDS and performance (expansion of VTOC position)
https://www.garlic.com/~lynn/2001d.html#64 VTOC/VTOC INDEX/VVDS and performance (expansion of VTOC position)
https://www.garlic.com/~lynn/2001l.html#40 MVS History (all parts)
https://www.garlic.com/~lynn/2002.html#5 index searching
https://www.garlic.com/~lynn/2002.html#6 index searching
https://www.garlic.com/~lynn/2002.html#10 index searching
https://www.garlic.com/~lynn/2002d.html#22 DASD response times
https://www.garlic.com/~lynn/2002f.html#8 Is AMD doing an Intel?
https://www.garlic.com/~lynn/2002g.html#13 Secure Device Drivers

In the mid-60s ... there were relatively scarce real storage and relatively abundant disk thruput. That started shifting in the early to mid 70s (as in the stuff about disk relative disk performance had declined by a factor of ten ... cpu & memory increased by factor of 40 to 50 but disk only increased by a factor of 4 to 5). recent post in this thread:
https://www.garlic.com/~lynn/2002l.html#29
&
https://www.garlic.com/~lynn/2001l.html#46
https://www.garlic.com/~lynn/2002e.html#8

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

IBM 2311 disk drive actuator and head assembly

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: IBM 2311 disk drive actuator and head assembly
Newsgroups: alt.folklore.computers
Date: Tue, 10 Sep 2002 20:47:32 GMT

"plonquemaster" writes:
Hey, I remember those things! didn't they have some kind of fluid-drive on the disk arm? Oil? Water? We had them in my shop in the early 1970s, and quickly replaced 'em with Telex drives which had newer voice-coil technology driving the arm. IBM did their darndest to prevent us switching to Telex - "It's unproven technology.. The cylinder tracking is gonna be terribly inaccurate", etc. The Telex drives actually were much more reliable than the clunky IBM 2311s, as I recall. I seem to recall Telex was formed by a disgruntled cadre of IBM engineers.

a little search engine, telex, dirty dozen, shugart, etc
http://www.disktrend.com/disk3.htm

once when i asked why was i being involved in channel architecture/interface issues? ... i was told so many of the senior engineers who knew the stuff had left.

random refs:
https://www.garlic.com/~lynn/subtopic.html#disk

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Handling variable page sizes?

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Handling variable page sizes?
Newsgroups: comp.arch
Date: Tue, 10 Sep 2002 21:45:11 GMT

robertwessel2@yahoo.com (Robert Wessel) writes:
In any event, the only S/370 OS that I know of that ever switched TF formats was VM, and it only supported 2KB and 4KB pages, and only 64KB segments (and 2KB pages only on real hardware that supported that size).

dos/vs and vs1 used 2k pages. vm nominally used 4k pages & 64k segments. mvs used 4k pages and 1mbyte segments. however, when VM was running a virtual relocate gues, it would use shadow tables that were the same as the guest (i.e. if the guest used 4k pages and 1mbyte segments, vm would run it with shadow tables that were 4k pages and 1mbyte segments).

there was a "incident" with 370/168 going from a 370/168-1 to a 370/168-3 where the cache was doubled from 32kbytes to 64kbytes.

one of the cache index lines for 64kbyte mode was the 2k bit. when running in 2k page mode ... a 168-3 only used half of the cache (32kbytes).

a customer was running dos/vs under vm on a 168-1 and they upgraded to 168-3 with 64kbyte cache. they not only didn't see any performance improvement, they actually saw a significant performance decrease ... aka vm would switch to 4k pages normally ... but would load 2k page mode for the vs1 shadow tables. in 2k page mode, only half the cache was used (same as original 168-1). However, every time there was a switch between 2k & 4k mode ... the complete cache had to be flushed since it used different bits for indexing the cache (i.e. stuff could be a different cache locations depending on whether 2k/4k page mode with a 168-3 64kbyte cache). This resulted in a 168-3 actually having noticeably worse performance than a 168-1.

About the virgil/tully (138/148) ecps time-frame there was also VS1-handshaking when running under VM .... where VS1 running under VM could actually run faster than if it was running on the bare hardware. In VS1-handshaking mode, VS1 could be given a 16mbyte virtual address space which it could treat almost as psuedo real. VM would run it with 4k virtual pages and VS1 would never do any of its own paging. There was this psuedo interrupt mode .... that if a VS1 application took a (VM) page fault .... VM kernel would do the appropriate thing ... and reflex a special virtual page fault interrupt to the VS1 kernel .... providing the VS1 kernel an opportunity to task-switch. The issue that VM's significnat more efficient management of 4k pages was so much better than VS1's management of 2k pages .... that it tended to more than compensate for the VM's hypervisor overhead.

The other issue on 165, 168, etc was the TLB. There was a 128-entry TLB with a seven entry "STO" stack. Effectively STO (segment table origin) is synonym for address space. TLB could have similar entries simultaneously for up to seven different address spaces .... before it would have to flush TLB entries to scavange for new TLB entries. 165/168 was primarily designed with MVS as the traditional use which had a design of a 16mbyte address space ... with 8mbytes dedicated for the supervisor and 8mbytes (possibly) available for application usage (aka MVS supervisor code was resident in the application address space). This originally was carry over from MVT non-virtual memory architecture with a single real address space occupied by the supervisor and all applications. The original conversion from MVT to relocate (SVS) was a single 16mbyte address space with essentially the MVT supervisor laid out in 8mbytes and all application sharing the remaining 8 mbytes. This was later enhanced to multiple address spaces (MVS) with a unique application for each application ... but the architecture retained the fact that a (common shared) MVS kernel still occupied the application address space. As an aside, there was subsequent problem with this as the MVS system &/or subsystem functions started to exceed 8mbytes ... and started to severely encroach on the 8mbyte space left for application addressing (paradigm was pointer passing with direct addressing .... not variable passing). Prior to 31bit support there was a hardware hack called dual-address support ... where a subsystem function was able to use pointer to access data in a different/secondary address space.

In any case, because of the SVS/MVS orientation with kernel occupying 8mbyte and application occupying 8mbyte ... the engineers chose the "8mbyte" bit as one of the bits for indexing the TLB; effectively partitioning half the 165/168 TLB entries for the MVS kernel and half for MVS applications (actually there were lots of duplicate kernel entries ... even tho the kernel code was shared/same in every address space ... TLB couldn't tell it since entries were identified by address space identifier). However, non-MVS environments (VM, VS1, DOS,VS, etc) tended to have very few environments with heavy use of >8mbyte virtual address .... so for them only half the (165/168) TLBs >were used.

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Itanium2 performance data from SGI

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Itanium2 performance data from SGI
Newsgroups: comp.arch
Date: Tue, 10 Sep 2002 21:55:00 GMT

Petter Gustad writes:
Is the current SGI NUMAlink HIPPI/GSN based?

i would believe it is proprietary.

HIPPI was originally parallel copper channel driven by LANL to have a cots/standard cray channel interface.

FCS was serial fiber driven by LLNL to have cots/standard for high-speed serial non-blocking switch (which i believe they originally had product that was copper).

SCI (scalable coherent interface) was fiber asynchronous interface for things like memory as cots/standard driven by guy from SLAC. SCI was used by (at least) sequent, data general, and in convex exemplar for their NUMA implementations.

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

10 choices that were critical to the Net's success

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: 10 choices that were critical to the Net's success
Newsgroups: alt.folklore.computers
Date: Tue, 10 Sep 2002 23:07:47 GMT

the '70s had a number of time-sharing services some with local telecom numbers .... tymshare/tymnet, ge, compuserve, etc ... plus various corporate internal networks. then there were the online services from at least late '60s ... not so much general time-sharing ... like dialog and NLM (national library of medicine). NLM started running into some of the current search engine scale-up issues around 1980 (huge database and strongly bimodal operation, 5-7 search terms still yielding hundreds of thousands of hits ... and adding one more qualifier and number of hits dropping to zero).

the time-sharing & online services had terminals dial into (possibly local) numbers and access facilities on mainframe (email, application, data sources, etc). today, some number consumers effectively interact in much the same way with browsers on their PCs acting as little more than fancy graphic terminals.

networking well into the 80s was still primarily multi-user machines ... where the end-user was getting services with a terminal (or terminal emulation). the translation of internet into the consumer market in the early '90s was the end-user interface providing similar type capabiilty that was available in the 70s via terminals connecting to time-sharing/online services.

in the early to mid 90s various online services were starting to look at internet support. for some of them, their issue was that they were supporting 40-50 different terminal emulation and modem driver packages for their customers (including trouble calls, setup operations, etc). Switch-over to the "internet" allowed them to offload all of that gorp onto the ISPs, a significant cost savings while effectively being able to provide the same/similar service. The ISPs saw tcp/ip as emerging standard that all personal computers and modem makers would support as single interoperable standard (effectively the same protocol was going to be used for the traditional multi-user service delivery, wide-area networking, and end-user "terminal" operation).

somewhat from telecom perspective there was

1) inter-machine "network" links between multi-user machines
2) end-user dial-up connections
3) pop concentrators that had some of the characteristics of #1.

as an aside, some of the registered ".com" domain names from a oct. 1990 list:
https://www.garlic.com/~lynn/2000e.html#20

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

10 choices that were critical to the Net's success

From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: 10 choices that were critical to the Net's success
Newsgroups: alt.folklore.computers
Date: Tue, 10 Sep 2002 23:37:07 GMT

for a random "early" reference on some of this

The Network Nation, Human Communication via Computer, Hiltz & Turoff, Addison-Welsley Publishing, 1978

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

The problem with installable operating systems

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: The problem with installable operating systems.
Newsgroups: alt.folklore.computers
Date: Wed, 11 Sep 2002 14:02:38 GMT

"Rostyslaw J. Lewyckyj" writes:
Once upon a time there was on the IBM 360, in the days of, I believe, early MVT, a thing called a fast IPL. After a system had been IPLed (current term is booted), one dumped the system image to a disk or tape. Then if one needed to restart the system, all that was needed was to reload this initial system image into memory and go. Note that what I am writing about here is not a warm start IPL versus a cold start. I mean just load the system core image and go. It seems to me that for the current systems the OS manu- facturers could perhaps provide something of that sort. Or at least provide something like a warm start IPL, or something in between. It would be up to the operator to choose which to use. If the software & hardware set up had not changed since the previous fast IPL had been built, then one could invoke that. If there had been a change, then a full IPL would be done. If the hardware needed some checking then the POST checks would be run. As it is each IPL is set up for maximum generality. Or so it seems to me. --Rostyk

i might claim that all came from CP/67 .... both CP and CMS standard effectively loaded everything into memory and then did memory save to disk. CP then had these things that were IPL-by-name .... additional capability that saved memory images (cp savesys command) to special area in the paging system. There was little difference between IPL'ing a CMS image off disk and ipl'ing a CMS image by name ... except IPL by name also allowed the ability to (optionally) specify specific pages that could be shared across all processes using the same IPL by name.

This was first used with some flavor of OS/360 PCP .... save a memory image of OS/360 at some point where it was quiesced ... and then later be able to IPL the image by name. It was then later used by lots of CP/67 installations for various images of MFT and MVT. It would have been a hack to include something in mft/mvt to provide a similar capability w/o cp/67. The original for PCP I believe was also used by a PCP shell written by somebody from union carbide that attempted to simulate some of the CMS features at the "opertor's console" (aka using wto, wtor, etc to provide some interactive services to what PCP thot was the 1052 operator's console).

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

10 choices that were critical to the Net's success

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: 10 choices that were critical to the Net's success
Newsgroups: alt.folklore.computers
Date: Wed, 11 Sep 2002 14:25:06 GMT

jmfbahciv writes:
Every TOPS-10 system sold to a university and government had dial-in. I first met one in 1969. So that's an earlier timestamp for general timesharing.

all of cp/67 had dial-in and general time-sharing ... but from the stnadpoint of commercial time-sharing or commerical online service ... in '68 some of the guys from CSC left and formed NCSS cp/67 time-sharing service (down in stamford, conn) ... and later that year a couple others from CSC and Lincolm Labs left and formed IDC cp/67 time-sharing service (out in waltham).

NCSS may still be remembered for nomad:
https://www.garlic.com/~lynn/2002i.html#64 Hercules and System/390 - do we need it?
https://www.garlic.com/~lynn/2002i.html#69 Hercules and System/390 - do we need it?

tymshare was formed later in the '70s with vm/370 (port of cp/67 to 370).

I was trying to think of other commercial time-sharing/online services. van vleck has story about CP/67 crashing at the MIT Urban Systems Lab (I think they were physically in the bldg. cross the courtyard from 545 tech sq ... 565? ... the one with harvard trust branch on the firts floor; tech sq had 3 towers, 545, 565?, and 5?? and then two story bldg that was occupied by land;). I believe the Urban Systems lab provide online service to various (fed, state, local) gov. accounts involved in urban planning.
https://www.garlic.com/~lynn/2001f.html#78
https://www.multicians.org/thvv/360-67.html

and of course ... various of the cp/40 & cp/67 people came over from CTSS which was the compatabile time-sharing system.

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Handling variable page sizes?

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Handling variable page sizes?
Newsgroups: comp.arch
Date: Wed, 11 Sep 2002 14:42:34 GMT

robertwessel2@yahoo.com (Robert Wessel) writes:
My memory must be failing here. I thought the common segment bit was already there on the 168s, or did that show up on the 303Xs? Or was this just a release of MVS that didn't use them yet?

CSA was effectively part of address space that could be used by subsystem that ran as an application in its own address space and share data with other subsystems. it was one of the things that tended to grow and encroach on available application space since it was in all address spaces ... just like the mvs kernel code (or could be used by some stub code to copy data into and then have used by applications or subsystem running in another address space).

dual-address space was something that showed up with 3033. it allowed subsystems to directly reach into a different address space. one of the things was to be able to cut down on growth in csa.

misc. dual-address space refs:
https://www.garlic.com/~lynn/2000c.html#84 Is a VAX a mainframe?
https://www.garlic.com/~lynn/2000e.html#58 Why not an IBM zSeries workstation?
https://www.garlic.com/~lynn/2001i.html#13 GETMAIN R/RU (was: An IEABRC Adventure)
https://www.garlic.com/~lynn/2002d.html#51 Hardest Mistake in Comp Arch to Fix
https://www.garlic.com/~lynn/2002g.html#17 Black magic in POWER5
https://www.garlic.com/~lynn/2002g.html#18 Black magic in POWER5

it then got even more complicated with access registers and program call. basically approx. the efficiency of a direct branch and link to some library code w/o having to interrupt into kernel supervisor code ... but do the call to code in different address space and with a somewhat different set of privileges.
https://www.garlic.com/~lynn/98.html#36 What is MVS/ESA?
https://www.garlic.com/~lynn/2001d.html#30 Very CISC Instuctions (Was: why the machine word size ...)
https://www.garlic.com/~lynn/2001h.html#73 Most complex instructions
https://www.garlic.com/~lynn/2001k.html#16 Minimalist design (was Re: Parity - why even or odd)
https://www.garlic.com/~lynn/2002d.html#51 Hardest Mistake in Comp Arch to Fix
https://www.garlic.com/~lynn/2002g.html#17 Black magic in POWER5

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Spin Loop?

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Spin Loop?
Newsgroups: bit.listserv.ibm-main
Date: Wed, 11 Sep 2002 15:06:01 GMT

GoHabsGo writes:
Sorry, this isn't really helping. Any other takers?

sounds like a homework assignment.

try search engine for compare and swap, test and set, and/or spin loops.

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Spin Loop?

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Spin Loop?
Newsgroups: bit.listserv.ibm-main
Date: Wed, 11 Sep 2002 15:17:29 GMT

Anne & Lynn Wheeler writes:
sounds like a homework assignment.

try search engine for compare and swap, test and set, and/or spin loops.

typically associated with various kinds of barriers ... might also try places like acm, ieee, or some of the university search engines related to papers on barrier semantics.

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Handling variable page sizes?

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Handling variable page sizes?
Newsgroups: comp.arch
Date: Wed, 11 Sep 2002 16:06:02 GMT

Per Ekman writes:
MIPS processors (at least the R4000) uses an Address Space Identifier (ASID) in each TLB-entry to factor in the PID (I think Alpha, ARM and IA-64 has something similar). Together with a page mask that specifies how many lower bits of the virtual page number to pass through to the physical address it enables each process to have its own page size. With 4KB pages (the smallest allowed) the least significant bit in the VPN selects the physical address from a set with two entries. If the page mask is used then the set reverts to a single entry.

as referenced in earlier on 165/168 .... it used a 7 entry (3 bit) STO-stack. Each TLB entry was tagged as being associated with one of the STO-stack entries or free/invalid. STO was segment table origin ... which was table in physical memory, the address got loaded into a control register to switch virtual address spaces. As part of loading, the address was checked against the STO-stack and if it already existed in the STO-stack ... then that ID was set as active. If it wasn't already in the STO-stack ... a LRU selection was done ... and all the corresponding TLB entries (with the replaced 3-bit ID) were reset to invalid.

801/ROMP with inverted tables ... had no unique table address for identifying address space. What it did instead was to define 16 (hardware) segment registers ... each segment register was loaded with a unique 12-bit segment identifier. The top four bits of a 32-bit address was used to select a segment register and the 12-bit segment identifier (from the segment register) was used to "tag" the (remaining 28bit) virtual address and was carried into the TLB. As a result, 801/ROMP instead of having virtual address space associated TLB entries ... had virtual segment associated TLB entries. A straight-forward unix implementation might have a totally unique address space with a set of 16 totally unique segment register values (i.e. each address space instead of having a single unique identifier, had 16 unique identifiers for each range of 256mbyte segments). A 256mbyte segment that was shared across multiple address spaces could have each own unique 12-bit segment identifier (and the TLB entries would only appear once for the shared segment, regardless of the number of address spaces it appeared in). Even tho 801/ROMP was a 32bit virtual address space .... sometimes there was documentation referring to 801/ROMP as having 40bit virtual addressing (low-order 28bits from the 32bit virtual address plus the 12bit unique segment identifier).

The unique segment identifier in 801/RIOS was expanded from 12bits to 24bits ... so you sometimes see documentation on RIOS referring to it having 52bit virtual address (low-order 28bits from the 32bit virtual address plust the 24bit unique segment identifier).

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

10 choices that were critical to the Net's success

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: 10 choices that were critical to the Net's success
Newsgroups: alt.folklore.computers
Date: Wed, 11 Sep 2002 18:49:33 GMT

greymaus writes:
I agree. There was an ancient database then called Digalog (or similiar word), started out as part of Boeing, AFAIk, amazingly cryptic, does it still live?

dialog part of lockheed ... sold a couple times ... i believe now owned by the publishing house that does san jose mercury news(?). HONE, Dialog, Tymshare, and SLAC datacenters were all in a couple miles of each other ... could make the rounds in an afternoon and then go to the oasis.

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Itanium2 performance data from SGI

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Itanium2 performance data from SGI
Newsgroups: comp.arch,alt.folklore.computers
Date: Wed, 11 Sep 2002 18:50:48 GMT

mailer-daemon@bof.de (Patrick Schaaf) writes:
For a pure CPU userlevel job, what percentage of real running time would you expect those bookkeeping tasks to consume?

Anybody ever used proper instrumentation to (gasp) measure this, instead of speculating? There's nice cycle and L2 cache miss counters to use for such instrumentation.

i've frequently claimed that one of the issues that got CP/67 (original virtual machine hypervisor) was that it was easy to see elapsed/cpu-use with and w/o the cp kernel. very few operating systems have had so much attention at the time ... because it wasn't easily possible to observe the effect of running with and w/o the supervisor/kernel.

the other was that the group responsible for cp/67 did a lot of instrumentation and performance related work. a lot of the early stuff that eventually matured into things like capacity planning went on at the cambridge science center. For ECPS ... deciding what pieces of the kernel to drop into m'code ... there was 1) sequence timing of specific paths, 2) m'code changes that implemented kernel address sampling ... to infer precent time spent in each portion of the kernel 3) multiple regression analysis, and 4) make some change in critical portion and run with and w/o the change to gauge aggregate effects. misc. recent ref regarding capacity planning:
https://www.garlic.com/~lynn/2001n.html#31 Hercules etc. IBM not just missing a great opportunity...
https://www.garlic.com/~lynn/2001n.html#32 Hercules etc. IBM not just missing a great opportunity...
https://www.garlic.com/~lynn/2002b.html#64 ... the need for a Museum of Computer Software
https://www.garlic.com/~lynn/2002c.html#11 OS Workloads : Interactive etc
https://www.garlic.com/~lynn/2002c.html#39 VAX, M68K complex instructions (was Re: Did Intel Bite Off More Than It Can Chew?)

ecps data (this was sorted by accumlative to select top 6000 bytes of instructions ... there was approx. 1:1 translation from 370 instruction bytes to m'code instruction bytes):
https://www.garlic.com/~lynn/94.html#21 370 ECPS VM microcode assist

one of the things that many of the unixes did was to implement something that woke up 60 to 100 times a second and use that sampling as measure of what process was running ... and perform some amount of the scheduling function at that time .... plus possibly another daemon that woke up once a second that performed the rest of the stuff.

The original CP/67 had the one second daemon (I wondered if both unix and cp/67 inherited that from ctss; ... unix by way of multics). However, cp/67 used a high resolution interval timer to measure both aggregate application time as well as aggregate kernel time spent on behalf of each application (application accounting would show "total cpu", "problem cpu", and "kernel cpu" ... so it was readily apparent how much cpu was spent in each applicationn as well as amount of cpu spent in the kernel on the behalf of each application). The original CP/67 also had "overhead" ... time spent in scheduling and task-selection that wasn't directly attributable to any specific task/application. This tended to increase super/non-linearly proportional to the number of concurrent address spaces/tasks ... and for 30 users easly hit 10 percent of total cpu.

When i rewrote and restructured a bunch of this code ... I eliminated the once a second demon as well as nearly all of the "overhead" (it became a trivial small fraction of a percent). There was some slight additional scheduling pathlength added to application processing at various state change events ... and was charged off directly to that application (instead of overhead) but it was only a trivial fraction what the wake-up overhead stuff had been and also nicely proportional to the activity rather than super-linearly proportional to the number of address spaces/tasks ... i also did fastpath, dynamic adaptive, fairshare, page replacement and a bunch of other algorithmic enhancements so tended to see the aggregate effects of a whole bunch of stuff, recent misc:
https://www.garlic.com/~lynn/2002g.html#32 Secure Device Drivers
https://www.garlic.com/~lynn/2002h.html#75 time again
https://www.garlic.com/~lynn/2002i.html#42 CDC6600 - just how powerful a machine was it?
https://www.garlic.com/~lynn/2002k.html#66 OT (sort-of) - Does it take math skills to do data processing ?
https://www.garlic.com/~lynn/2002l.html#4 why is Kerberos better than this simpler replacement
https://www.garlic.com/~lynn/2002l.html#25 Do any architectures use instruction count instead of timer
https://www.garlic.com/~lynn/2002l.html#39 Moore law
https://www.garlic.com/~lynn/subtopic.html#fairshare
https://www.garlic.com/~lynn/subtopic.html#wsclock

There was actually a number of reasons for eliminating the fixed wakup stuff ... one of the reasons had to do with customer leasing of machines (based on hours metered/used). There was a "active" meter that customers got charged for use of the leased machine. The meter ran whenever there was active I/O or whenever the CPU was executing cycles. One of the first things that got changed was how terminal I/O was handled ... a special I/O command for terminals was used that would wait/prepare (rather than read time-out) for data transmission from the terminal. The use of this had the effect of looking like no I/O was active as far as the cpu metering was concerned.

The other characteristic was that the meters tended to "coast" for something like 400ms, aka if the meter ticked at all, it would then tick for a minimum of 400 milliseconds. Changing the stuff so things ticked only when absolutely necessary significantly descreased the metering charges for running 7x24 online, general time-sharing service (leave the service up and available 7 days a week, 24hrs a day, even during periods when there was only light or no load).

the 3rd thing which also helped with being able to offer 7x24 online, general service was automated operator .... automating many of the things that previously required that a human be physically present at the machine at all times (aka run dim/dark room operations 3rd & 4th shifts).

misc. cpu meter stuff:
https://www.garlic.com/~lynn/99.html#86 1401 Wordmark?
https://www.garlic.com/~lynn/2000b.html#77 write rings
https://www.garlic.com/~lynn/2000d.html#40 360 CPU meters (was Re: Early IBM-PC sales proj..
https://www.garlic.com/~lynn/2000d.html#42 360 CPU meters (was Re: Early IBM-PC sales proj..
https://www.garlic.com/~lynn/2002k.html#64 History of AOL

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

10 choices that were critical to the Net's success

From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: 10 choices that were critical to the Net's success
Newsgroups: alt.folklore.computers
Date: Wed, 11 Sep 2002 19:14:40 GMT

jmfbahciv writes:
Every TOPS-10 system sold to a university and government had dial-in. I first met one in 1969. So that's an earlier timestamp for general timesharing.

slightly related to general/commercial time-sharing offering is the later half of cross-post from comp.arch:
https://www.garlic.com/~lynn/2002l.html#62 Itanium2 performance data from SGI

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

10 choices that were critical to the Net's success

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: 10 choices that were critical to the Net's success
Newsgroups: alt.folklore.computers
Date: Wed, 11 Sep 2002 19:41:34 GMT

greymaus writes:
I agree. There was an ancient database then called Digalog (or similiar word), started out as part of Boeing, AFAIk, amazingly cryptic, does it still live?

boeing did something else ... in early '69 they formed BCS ... which was going to take-over nearly all internal boeing computer operations ... and run it as a service both for internal operations but also offer services externally. i was still an undergraduate ... but they con'ed me into teaching a one week system class for the BCS technical staff during spring break ... and then they hired me for the summer (it was classified as a full-time position even tho it was only for the summer, I was bcs employee number 20 or 30 something) to setup and put into production a CP/67 time-sharing service. This was possibly the original real computer in BCS ... because there was still various kinds of internal politics about the head of BCS getting the various datacenter heads to report to him.

I believe there was something relatively recently about boeing sold bcs to SAIC.

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

The problem with installable operating systems

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: The problem with installable operating systems.
Newsgroups: alt.folklore.computers
Date: Thu, 12 Sep 2002 15:21:02 GMT

"Rostyslaw J. Lewyckyj" writes:
You write "i might claim that all came from CP/67 ...." Perhaps you might enlighten me with the dates for PCP and CP/67 and VM. Why do you claim that for MFT or MVT, fast IPL would have been "a hack" w/o cp/67? A hack it may have been, but where does cp/67 come in? --Rostyk

CP/40 was done by the ibm cambridge science center in 65 ... port to 360/67 was done in '67. some ibm'ers came out and installed it at the university i was at like the 3rd week in jan. '68 (it was the first official installation outside cambridge ... although i believe mit lincoln labs may have played with it a little in late '67). IBM announced it at the spring '68 SHARE meeting in houston ... i got to be part of the announcement since i had been playing since they had installed it.

in addition to a number of customers installing cp/67 during 1968, a number of internal IBM locations installed it for internal IBM development work. I had heard presentations by both customers and internal ibm locations making presentatons about doing CP/67 "savesys" of MFT & MVT systems. The internal ibm locations seemed to have multiple OS/360 copies running simultaneously for different development work. The fast-ipl with savesys cut elapsed time of doing developement, crash, restart, etc ... of multiple people with their own private copy of the operating system doing various kinds of development. There may have been as many (or more) internal IBM datacenter installations of CP/67 as all customer installations (because of its utility for doing various kinds of development).

CP/67 provided the function for savesys and ipl-by-name as part of the operating system support .... so i would suspect that if stand-alone MVT didn't initially have it as part of the base operating system ... somebody would have had to write the code (aka a hack ... or at least according to the original definition of hack). In any case, some number of things seemed to have flowed out of the os/360 development activities after first being used in a CP/67 environment (aka some MVT developer having seen how easy it was for CP/67 & CMS to do fast-ipl as well as how useful ipl-by-name was for os/360 operation ... decided to look at if it was possible to do something similar for native MVT in a non-CP/67 environment).

It was also seen in utility for AOS/SVS development. There were a number of places that had defined 16mbyte virtual machines for MVT under CP/67 and ran it with some psuedo-interrupt for page-fault handshaking (something seen later in the official VM/370 product for VS1). Effectively, AOS/SVS was much the same thing but w/o CP/67 and some additional restructuring of the MVT kernel. I vaguely remember being in the 706 machine room (I had graudated and was working at cambridge science center) and Ludlow(?) had taken a hacked version of CCWTRANS (the routine that did the translation of virtual->real addresses for I/O and fixed the pages while the i/o was active) and integrated it into native hacked MVT kernel was part of the early aos/svs development.

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

10 choices that were critical to the Net's success

Refed: **, - **, - **, - **, - **

From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: 10 choices that were critical to the Net's success
Newsgroups: alt.folklore.computers
Date: Thu, 12 Sep 2002 15:30:39 GMT

jmfbahciv writes:
First Data in Waltham? I don't know how much of their service was available to dialin the way we know it today. Most people didn't want to have anything to do with computers, so they contracted out for those services. Then people wanted to "own" their own gear to keep control of their data, so those rich enough started up their own internal computer centers. I think this is about when the -10s started catching on. Caveat: this is mere speculation on my part.

IDC in waltham (Interactive Data Corporation ... a different IDC than the report/study company) they were the 2nd CP/67 service bureau with some cambridge and lincoln labs people. In the '70s there were big into online stock & financial data analysis (do 100 year history analysis of publicly traded corporations).

FDC is totally different company that started in the midwest in the early '70s doing various kinds of bank data processing outsourcing. They were bought up by Amex in the early '80s and then spun-off as "FDC" in '92 (up until then the largest IPO spin-off, since dwarfed by all the dot.com stuff).

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

The problem with installable operating systems

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: The problem with installable operating systems.
Newsgroups: alt.folklore.computers
Date: Thu, 12 Sep 2002 15:51:47 GMT

Anne & Lynn Wheeler writes:
It was also seen in utility for AOS/SVS development. There were a number of places that had defined 16mbyte virtual machines for MVT under CP/67 and ran it with some psuedo-interrupt for page-fault handshaking (something seen later in the official VM/370 product for VS1). Effectively, AOS/SVS was much the same thing but w/o CP/67 and some additional restructuring of the MVT kernel. I vaguely remember being in the 706 machine room (I had graudated and was working at cambridge science center) and Ludlow(?) had taken a hacked version of CCWTRANS (the routine that did the translation of virtual->real addresses for I/O and fixed the pages while the i/o was active) and integrated it into native hacked MVT kernel was part of the early aos/svs development.

POK, KNG, ENG, etc were using CP/67 as internal platform for development ... both for testing in the virtual machine capability as well as heavy use of CMS for things like test/source editing. The 360 (then 370) principles of operation was one of the first documents converted to CMS script (first the dot run-off type stuff ... and then gml). Part of the reason for the POP being converted to cms script was that there were actually two versions ... the "red-book" version (which had all the interesting internal comments, detailed justifications, trade-off discussions, unannounced stuff, etc) and the POP version. The POP version was a subset of the red-book with all the red-book stuff selected out.

In any case, when the virtual memory stuff for 370 started .... not only was CP/67 an internal tool for various kinds of development testing as well as online use .... but it was one of the major sources of knowledge about virtual memory operation (both production running code as well as people with experience about virtual memory). CP/67's CCWTRANS module was an example of how to examine ccw strings, do virtual->real translation, fix/pin pages, unfix/unpin pages when operations were complete. clean-up, etc.

It was something like 3-4 hrs drive from boston to POK ... get up around 4 or 5am ... and hit the road, out the mass pike and then down the taconic parkway. some number of us got to do it for awhile.

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

10 choices that were critical to the Net's success

Refed: **, - **, - **

From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: 10 choices that were critical to the Net's success
Newsgroups: alt.folklore.computers
Date: Thu, 12 Sep 2002 16:35:07 GMT

jmfbahciv writes:
JMF's very first project (the one DEC hired him for) was to get a TOPS-10 system installed at ORNL. They lived in hotels for 3 or 6 months down there and spent a lot of time trying to get various other flavors of CPUs to "talk" to the -10 and visa versa. This was the fledging computer center that later grew into the 5-CPU SMP system. A lot of that system was used to run batch jobs that were set up on an IBM system. But all that tech detail is just a haze of war stories; I don't know how much is correct.

ONR (not ORNL) was conduit for lots of univerisity grants. the university i was at got a ONR grant to do an online library (card catalogue) system. For some reason, university got to be the beta-test for the original CICS as part of the ONR library grant. One of the library people got sent to some sort of CICS education ... and I got assigned to help him. I remember shooting CICS bugs ... sitting there asking him what did they tell you that this was suppose to do ... and then figuring out what the bug was and how to fix it.

(much, 25 plus years) later taking to the national library of medicine people (the two guys that had done the original work were still there), turns out that they were doing similar work at about the same time .... although their implementation was much more elegant and complex (they had much larger collection and eventually the whole world as their clients).

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

The problem with installable operating systems

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: The problem with installable operating systems.
Newsgroups: alt.folklore.computers
Date: Thu, 12 Sep 2002 17:18:09 GMT

the other reason for some number of the trips out the mass pike and down the taconic (besides all the virtual memory stuff coming for 370) was all the work that Cambridge had done in the area of symmetrical multiprocessor. Charlie had invented the compare&swap instruction (in part because various deficiencies with test&set semantics) and cambridge was lobbying hard to get it into 370 architecture; in fact, CAS was originally chosen as the mnemonic because they are charlie's initials ... and then the chore was to come up with something that matched his initials. That got lost a little when it was decided to do both a single word and a double word version of compare&swap and the CAS mnemonic was changed to CS and CDS.

the task that the 360/370 architecture group (aka smith & padegs owned the "redbook") gave cambridge for getting CAS into 370 was come up with paradigm/description that utilized CAS in uniprocessor environment (not just restricted to serialize/syncronnize multiprocessor). That gave rise to the original programming notes for CS/CDS on how they could be used for generalized multi-threaded application environment (in part eliminating the need for kernel calls for many multi-threaded operations). That section was originally published in the programming notes for the instruction. I believe it has since been moved to the appendix of the POPl.

random csc/545 tech sq postings:
https://www.garlic.com/~lynn/subtopic.html#545tech

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Al Gore and Fidonet [was: 10 choices]

Refed: **, - **, - **

From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Al Gore and Fidonet [was: 10 choices]
Newsgroups: alt.folklore.computers
Date: Thu, 12 Sep 2002 20:56:53 GMT

Floyd Davidson writes:
It was inter-networking, which Cerf and Kahn came up with in the early/middle 70's, that is significant. Gore's support started, roughly in 1976/7) after the basic concepts had been formed. His support in Congress grew larger and larger as the political requirements became more significant (i.e. in the '80s). I'm not sure that "forcing it out of the hands of the government" is quite the right terminology, but certainly Gore facilitated taking it private.

want there some bill around '80 that allowed gov. patents, technology and funded technology to easily leak into the commercial sector ... including promoting TRP-like programs. the other was allowing various technology consortiums and standards bodies to be exempt from some of the anti-trust provisions (groups of industry companies coming together to jointly decide on anything).

note that darpa, arpa, onr, and lots of other federal programs did enormous amounts of technology funding ... networking may have been one of the more minior ones. when i was an undergraduate in the '60s, i worked on an online library program funded by onr.

reference to federal technology transfer site (from same discussion two years ago)
https://www.garlic.com/~lynn/2000f.html#44

technology transfer legislative history web site (going back to 1980):
http://www.dtic.mil/techtransit/refroom/laws/

note that the first one list here is the bayh-dole acto of 1980
http://www.dtic.mil/techtransit/refroom/laws/t2_law_links.html

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

Faster seeks (was Re: Do any architectures use instruction

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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Faster seeks (was Re: Do any architectures use instruction
count instead of timer interrupts  for context changes?)
Newsgroups: comp.arch
Date: Thu, 12 Sep 2002 20:33:19 GMT

"Stephen Fuld" writes:
Perhaps, but there are lots of "way beyond today's cost effective reasonable DRAM size memory" data bases that are not this way.

For example, in the mid 1990s I had occasion to see a system being tested for the data warehouse of IIRC K-mart. It was 4-5 terrabytes and held essentially sales transaction data.

According to a presentation I heard from Jim Gray, Google is currently about 2 petabytes (WOW!) and, while there is a lot of graphics, I wouldn't think of it as data streams. Lots of banks, insurance companies, etc. have multiple terrabytes of database data that is not multi media oriented.

To there is still a need for fast, random access storage devices for much higher volumes than is cost effective for DRAMs. And you still have the volatility issue with DRAMS to overcome.

one of the original issues/problems getting relational database out as product is that the underlying index structure tended to (at least) double the physical disk space compared to earlier phyiscally indexed database (this is of the more traditional text oriented &/or account-based information). There was almost religous issue with the existing database people in STL ... System/R pretty much had to go thru the technology transfer from SJR to Endicott for SQL/DS before the reverse transfer from Endicott back to STL for DB2 (even tho SJR & STL are only about five miles apart on the west coast and Endicott is on the east coast). one of the people in the referenced meeting claimed to have done much of the SQL/DS->DB2 transfer:
https://www.garlic.com/~lynn/95.html#13

as the body of information grows and the data structures become much less uniform, the indexed related physical space can easily grow to 90 percent of physical space. Graphics, multimedia and/or other less compact data representation could somewhat offset that ratio, but in general, the physical keeping of complex relational information (as opposed to relational database relations which are implicit) can become a significant amount of the total physical space.

this is seen in other ways with the vaguries of RDBMS regular structure attempting to adapt to complex, real world information (rather than say simple account number index, account-based transactions). one large institution claimed to have over 6,500 RDBMS where 90-95 percent of the data was common across all the RDBMS (aka each RDBMS defined its own slightly different, regular, implicit relations). If you just count the total physical space for a single non-replicated copy of each piece of information against the total physical space for all 6,500 RDBMS implementations .... the ratio of actual information to total physical space is negligible.

i do a little of complex relations in the ietf RFC standards index stuff that i maintain at
https://www.garlic.com/~lynn/rfcietff.htm

in order to simulate the complex, bi-directional relation ... i generate a subset with various HTML representations and href pointers.

a similar case holds for the merged taxonomies & glossaries stuff (aka merged financial with >6000 terms, >8000 definitions and >28,000 hrefs)
https://www.garlic.com/~lynn/index.html#glossary

the count of characters devoted to HTML href stuff far exceeds the count of characters of actual data.

The other thing that goes on for some of the data warehouses with MDBS (multi-dimensional databases) is that they take the raw transaction database and pre-calculate a huge number of statistics and distributions for all the questions that anybody might ask. Possibly nightly or weekly ... they then update all the statistics with the most recent transaction data. If the domain of questions is fairly constrained with respect to the total data being processed ... then the answer batched precalculation can be a significant savings compared to effectively reading the whole set of transactions dynamically for every query. The MDBS physical space for the pre-calculated answers can easily be (much) larger than the raw transaction information.

Two possible extremes we've looked at in the past ... 1) a terabyte database of approx. 4k byte records that had 400,000 inserts and updates per day (airline) and a petabyte database of 1-10mbyte records that had possibly 4,000 inserts and updates per day (nasa).

--
Anne & Lynn Wheeler | lynn@garlic.com - https://www.garlic.com/~lynn/

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