From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: DASD Response Time (on antique 3390?) Newsgroups: bit.listserv.ibm-main,alt.folklore.computers Date: Thu, 24 Aug 2006 13:27:17 -0600re:
part of this is global cache/lru vis-a-vis local cache/lru. i had been
doing global cache management nearly 40 years ago in cp67 ... at the
time when at least some of the academic literature was focused on
local lru and effectively partitioned cache operation. numerous past
posts mentioning global LRU stuff
https://www.garlic.com/~lynn/subtopic.html#wsclock
the detailed file i/o cache modeling mentioned in the ref. thread posting ... basically found that (all things otherwise being equal), for a given amount of aggregate electronic memory, a global, non-partitioned cache was more effective than any partitioning the same amount of electronic memory.
earlier this week, in several hotchip presentations on multi-core designs, there were similar claims. L1 caches were effectively partitioned/local to a specific core. the scenario here was that latency issues negated the "condition" of all other things being equal. however, the larger L2 caches were non-partitioned, global, shared ... effectively the latency being equal between L2 and all cores.
another counter example ... to "all things otherwise being equal" was numerous previous postings about cluster 4341 configurations compared to 3033. six clustered 4341s with 16mbytes each (96mbytes aggregate), six i/o channels each (36 channels aggregate) had higher aggregate mip rate than 3033 with 16 i/o channels and 16mbytes memory ... at about the same price.
the disk i/o bottleneck and the limited real storage on the 3033 (to use as compensation for the disk i/o bottleneck) was one of the things that prompted the 32mbyte real storage "hack" offering for the 3033. even though standard 370 addressing (both real and virtual) was limited to 24bits (16mbytes). the 370 page table entry had 16bits, 12bit real (4k) page number (12bit virtual page * 12bit virtual page number yields 24bit virtual addressing), two "flag" bits, and two unused bits. the two unused bits were re-assigned so that they could be concatenated with the 12bit real page number to allow specification of up to 14bit (14bit*12bit=26bit or up to 64mbyte real addressing). instructions (both real and virtual) couldn't address more than 24bits ... but this hack allowed being able to utilize more than 16mbytes of real storage (for virtual pages belonging to multiple different address spaces).
previous mentioning the clustered 4341 vis-a-vis 3033 and/or the 3033
32mbyte real storage hack:
https://www.garlic.com/~lynn/95.html#3 What is an IBM 137/148 ???
https://www.garlic.com/~lynn/99.html#7 IBM S/360
https://www.garlic.com/~lynn/2000c.html#83 Is a VAX a mainframe?
https://www.garlic.com/~lynn/2000d.html#7 4341 was "Is a VAX a mainframe?"
https://www.garlic.com/~lynn/2000d.html#12 4341 was "Is a VAX a mainframe?"
https://www.garlic.com/~lynn/2000d.html#82 "all-out" vs less aggressive designs (was: Re: 36 to 32 bit transition)
https://www.garlic.com/~lynn/2000e.html#57 Why not an IBM zSeries workstation?
https://www.garlic.com/~lynn/2001b.html#69 Z/90, S/390, 370/ESA (slightly off topic)
https://www.garlic.com/~lynn/2001j.html#3 YKYGOW...
https://www.garlic.com/~lynn/2001l.html#32 mainframe question
https://www.garlic.com/~lynn/2001m.html#15 departmental servers
https://www.garlic.com/~lynn/2001n.html#39 195 was: Computer Typesetting Was: Movies with source code
https://www.garlic.com/~lynn/2002d.html#7 IBM Mainframe at home
https://www.garlic.com/~lynn/2002d.html#51 Hardest Mistake in Comp Arch to Fix
https://www.garlic.com/~lynn/2002f.html#8 Is AMD doing an Intel?
https://www.garlic.com/~lynn/2002i.html#22 CDC6600 - just how powerful a machine was it?
https://www.garlic.com/~lynn/2002i.html#23 CDC6600 - just how powerful a machine was it?
https://www.garlic.com/~lynn/2002n.html#58 IBM S/370-168, 195, and 3033
https://www.garlic.com/~lynn/2002n.html#63 Help me find pics of a UNIVAC please
https://www.garlic.com/~lynn/2003f.html#56 ECPS:VM DISPx instructions
https://www.garlic.com/~lynn/2003g.html#22 303x, idals, dat, disk head settle, and other rambling folklore
https://www.garlic.com/~lynn/2004g.html#20 Infiniband - practicalities for small clusters
https://www.garlic.com/~lynn/2004l.html#10 Complex Instructions
https://www.garlic.com/~lynn/2004m.html#17 mainframe and microprocessor
https://www.garlic.com/~lynn/2004n.html#14 360 longevity, was RISCs too close to hardware?
https://www.garlic.com/~lynn/2004n.html#50 Integer types for 128-bit addressing
https://www.garlic.com/~lynn/2004o.html#57 Integer types for 128-bit addressing
https://www.garlic.com/~lynn/2005.html#34 increasing addressable memory via paged memory?
https://www.garlic.com/~lynn/2005.html#43 increasing addressable memory via paged memory?
https://www.garlic.com/~lynn/2005f.html#4 System/360; Hardwired vs. Microcoded
https://www.garlic.com/~lynn/2005n.html#11 Code density and performance?
https://www.garlic.com/~lynn/2005n.html#29 Data communications over telegraph circuits
https://www.garlic.com/~lynn/2005p.html#1 Intel engineer discusses their dual-core design
https://www.garlic.com/~lynn/2005p.html#19 address space
https://www.garlic.com/~lynn/2005q.html#30 HASP/ASP JES/JES2/JES3
https://www.garlic.com/~lynn/2005q.html#38 Intel strikes back with a parallel x86 design
https://www.garlic.com/~lynn/2005s.html#22 MVCIN instruction
https://www.garlic.com/~lynn/2005u.html#40 POWER6 on zSeries?
https://www.garlic.com/~lynn/2005u.html#44 POWER6 on zSeries?
https://www.garlic.com/~lynn/2005u.html#48 POWER6 on zSeries?
https://www.garlic.com/~lynn/2006b.html#28 Multiple address spaces
https://www.garlic.com/~lynn/2006b.html#34 Multiple address spaces
https://www.garlic.com/~lynn/2006b.html#39 another blast from the past
https://www.garlic.com/~lynn/2006i.html#33 virtual memory
https://www.garlic.com/~lynn/2006i.html#41 virtual memory
https://www.garlic.com/~lynn/2006l.html#2 virtual memory
https://www.garlic.com/~lynn/2006l.html#18 virtual memory
https://www.garlic.com/~lynn/2006m.html#27 Old Hashing Routine
https://www.garlic.com/~lynn/2006m.html#32 Old Hashing Routine
https://www.garlic.com/~lynn/2006m.html#37 Curiosity
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: Greatest Software Ever Written? Newsgroups: alt.folklore.computers Date: Fri, 25 Aug 2006 10:00:06 -0600Brian Inglis writes:
so assembler is full of conditional branches ... and with a little analysis can be turned into higher level constructs, if/then/else, do/while, do/until, computed/case, etc (as opposed to emulated GOTOs).
the problem for some highly optimized kernel routines (implemented in assembler) ... the original GOTO-flavor (with conditional branches) could be significantly more understandable than some of the abstracted if/then/else, etc representations ... in one or two cases a relatively straight forward routine with a couple hundred machine instructions would translate into if/then/else infrastructure nested 20 deep. I finally had to put in a limit that would limit nested structures to no more than 10-15 deep.
part of the issue with GOTOs ... that i later tried to capture with
my dump analyzer
https://www.garlic.com/~lynn/submain.html#dumprx
was reconstructing code flow leading up to a fault (sort of program flow reconstructure or forensics). branch/goto implementations frequently would result in a lot of ambiquity as to exact execution flow arriving at a fault location. things like if/then/else construction would somewhat explicitly identify dependencies involved in particular execution paths ... and frequently helps in program comprehension.
however, i was surprised at the number of instances involving highly optimized assembler code ... where the if/then/else forms actually decreased comprehension (and the branch/goto forms were actually much easier to understand).
since then i've had a number of occasions, in non-assembler, highly optimized code sections, to use GOTO's as the most straight-forward implementation and ease of understanding.
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Overweight truckers stopped by tech checks Newsgroups: alt.folklore.computers Date: Fri, 25 Aug 2006 14:59:17 -0600somewhat a followup to old thread
Overweight truckers stopped by tech checks
http://www.silicon.com/retailandleisure/0,3800011842,39161811,00.htm
from above:
One axle overloaded by one tonne can cause the same road wear as 18,000 Mondeos.
...
Vosa is using the Viper service to spot and stop overweight
vehicles. The system combines Automatic Number Plate Recognition
(ANPR) and Weigh-In Motion System (Wims) technologies - electronic
strips set into the road surface.
... snip ...
old thread mentioning road lifetime design predicated on heavy
truck usage:
https://www.garlic.com/~lynn/2006g.html#5 The Pankian Metaphor
https://www.garlic.com/~lynn/2006g.html#6 The Pankian Metaphor
https://www.garlic.com/~lynn/2006g.html#10 The Pankian Metaphor
https://www.garlic.com/~lynn/2006g.html#12 The Pankian Metaphor
https://www.garlic.com/~lynn/2006g.html#15 The Pankian Metaphor
https://www.garlic.com/~lynn/2006g.html#19 The Pankian Metaphor
https://www.garlic.com/~lynn/2006g.html#24 The Pankian Metaphor
https://www.garlic.com/~lynn/2006g.html#26 The Pankian Metaphor
https://www.garlic.com/~lynn/2006g.html#32 The Pankian Metaphor
https://www.garlic.com/~lynn/2006g.html#35 The Pankian Metaphor
https://www.garlic.com/~lynn/2006g.html#46 The Pankian Metaphor
https://www.garlic.com/~lynn/2006g.html#48 The Pankian Metaphor
https://www.garlic.com/~lynn/2006g.html#49 The Pankian Metaphor
https://www.garlic.com/~lynn/2006g.html#50 The Pankian Metaphor
https://www.garlic.com/~lynn/2006g.html#51 The Pankian Metaphor
https://www.garlic.com/~lynn/2006g.html#52 The Pankian Metaphor
https://www.garlic.com/~lynn/2006g.html#53 The Pankian Metaphor
https://www.garlic.com/~lynn/2006g.html#54 The Pankian Metaphor
https://www.garlic.com/~lynn/2006g.html#56 The Pankian Metaphor
https://www.garlic.com/~lynn/2006g.html#57 The Pankian Metaphor
https://www.garlic.com/~lynn/2006g.html#59 The Pankian Metaphor
https://www.garlic.com/~lynn/2006g.html#60 The Pankian Metaphor
https://www.garlic.com/~lynn/2006g.html#61 The Pankian Metaphor
https://www.garlic.com/~lynn/2006g.html#62 The Pankian Metaphor
https://www.garlic.com/~lynn/2006h.html#0 The Pankian Metaphor
https://www.garlic.com/~lynn/2006h.html#5 The Pankian Metaphor
https://www.garlic.com/~lynn/2006h.html#6 The Pankian Metaphor
https://www.garlic.com/~lynn/2006h.html#11 The Pankian Metaphor
https://www.garlic.com/~lynn/2006h.html#23 The Pankian Metaphor
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: processors of the future: super-computer-on-a-chip? Newsgroups: comp.arch Date: Fri, 25 Aug 2006 17:05:25 -0600"Gary" writes:
one of the presentations said that they worked on the (parallel) programming paradigm for a long time before starting to define massive number of cores (on a chip) that would then fit the programming paradigm ... rather than the other way around ... building a massive number of cores and then trying to stumble across a programming paradigm that fit the cores.
session one ... had chips specifically designed to handle streaming.
session four on reconfigurable computing had a chip from toshiba with large number of cores that could be dynamically reconfigured
session five on parallel processing had a number of flavors of large number of cores on a chip.
http://www.hotchips.org/hc18/program/conference_day_one.htm
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: Greatest Software Ever Written? Newsgroups: alt.folklore.computers Date: Sat, 26 Aug 2006 07:34:26 -0600Andrew Swallow writes:
the abstraction had code blocks that were sequential sequence of instructions ... a code block could be bracketed by control flow leaving and/or code flow entering (from unconditional or conditional branch instructions). code blocks could be sequentially aggregated if they were connected by a single unconditional branch ... i.e. the branched-to code block was entered by only a single unconditional branch.
conditional execution was a pair of condition setting instruction followed by a conditional branch. a sequence of such instruction pairs could be collapsed into a single conditional execution statement abstraction ... as long as the conditional "to" location for all conditional branches was the same ... and there were no other intervening instructions between the conditional branching operations.
the issue with some highly optimized kernel paths was that they actually did a complex set of condition testing/branching ... with various intervening instructions. it wasn't just a sequence of multiple condition testing with no other intervening instructions and all the conditional branches having the same target. some kernel paths might be possible 1/3rd instructions condition testing/conditional branching with a mixed of target branch locations and arbitrary intervening instructions (both between sequences of conditional execution instructions and between branch target locations).
so a possible instruction sequence
test condition1
cond branch A
inst1
inst2
inst3
branch B
A test condition2
cond branch B
inst4
inst5
inst6
B ....
so w/o elseif it would be
if not condition1 then
inst1
inst2
inst3
else
if not condition2 then
inst4
inst5
inst6
end
end
so that can collapses into
if not condition1 then
inst1
inst2
inst3
elseif not condition2 then
inst4
inst5
inst6
end
however if the sequence at A was
A inst9
testing condition2
cond branch B
inst4
inst5
inst6
B ....
it really becomes nested ... the subsequent conditional testing/branch
has to be at code block boundary of the previous code block ... w/o
any other intervening instructions. the problem was that there was
some amount of highly optimized kernel pathlengths that exhibited that
characteristic ... potentially to the nested depth of 20. the
collapsing of condition boundaries like multiple conditions for a
single if statement and/or constructs like elseif ... had to have
specific semantics/boundaries for the conditional executed code
blocks.
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: sorting Newsgroups: alt.folklore.computers Date: Sat, 26 Aug 2006 08:26:26 -0600krw writes:
the lead-off break light in the accordion effect may not have touched their pedel sufficient to actually change speed ... just enuf to signal to the drivers behind.
i've been in certain traffic flows where the rapid lane change and accordion effect happened multiple times over a 10-15 mile interval .... i.e. the accordion clears, the traffic resumes to nearly speed limit ... and then another rapid lane change cauases it to repeat.
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: Admired designs / designs to study Newsgroups: comp.arch Date: Sat, 26 Aug 2006 08:51:46 -0600haynes@alumni.uark.edu (Jim Haynes) writes:
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: SSL, Apache 2 and RSA key sizes Newsgroups: sci.crypt,comp.infosystems.www.servers.unix Date: Sun, 27 Aug 2006 09:03:49 -0600Nelson B writes:
original e-commerce scenario was that SSL bracketed your whole session with the server ... from the initial connection, thru shopping and checkout. however, most e-commerce servers quickly found out that running SSL for the whole shopping experience dropped thru thruput by 80-90 percent ... and so most of them dropped SSL back to just being used for the payment process. Now you typically click on a payment button ... where the server provides the SSL URL ... and then the browser checks the domain name in the URL provided by the server against the URL in the certificate provided by the server (no longer is the process verifying that the server is the server you thot it was, but SSL is now verifying that the domain name that the server claims to be is the domain name that the server claims to be).
the original theory of digital certificates is that domain name that
you provided matches the domain name in the provided digital
certificate as a countermeasure to things like man-in-the-middle
attacks. however, if the server is providing both the URL (and
therefor the domain name) as well as the digital certificate ... it is
no longer a countermeasure to man-in-the-middle attacks ... and
therefor becomes redundant and superfluous. the server might just as
well as be directly transmitting its public key ... with none of the
PKI and digital certificate armoring. misc. past posts mentioning
MITM-attacks
https://www.garlic.com/~lynn/subintegrity.html#mitm
"i claim to be some arbitrary entity" ... and then provide a digital certificate that confirms that "i'm whoever" it is that "i claim to be". the current browser and end-user don't typically look at whoever it is that I claim to be ... the infrastructure is just relying on the browser to confirm that I have any digital certificate that supports whatever claim that i happen to be making.
misc. past posts mentioning various ssl certificate subjects
https://www.garlic.com/~lynn/subpubkey.html#sslcert
past mention of being asked to consult with this small client/server
startup that wanted to do payments on their server ... and wanted to
have something that came to be called a payment gateway ... and had
this technology called ssl
https://www.garlic.com/~lynn/aadsm5.htm#asrn2
https://www.garlic.com/~lynn/aadsm5.htm#asrn3
so another issue related to ssl domain name certificates was that when an entity applies to a certification authority for a ssl domain name certificate ... the certification authority requires a lot of identification information. they then check with the authoritative agency responsible for domain name owners ... the domain name infrastructure ... for identification information about the domain name owner. they then try and determine if the identification information on file with the domain name infrastructure appears to map to the same entity as the identification informaton provided by the ssl domain name certificate applicant.
there has been some concern as to possible compromises in the identity information on file with the trust root for domain name ownership ... the domain name infrastructure. so a proposal somewhat backed by the certification authority industry is to have domain name owners register a public key at the same time as they register their domain name. then the certification authority industry can request that ssl domain name certificate applications be digitally signed. then the certification authority can change from an expensive, time-consuming and error-prone identification process to a much less expensive, reliable and efficient authentication process by retrieving the public key from the domain name infrastructure to verify the digital signature on the ssl domain name certificate application.
the problem is that this then represents something of a catch-22 for the certification authority industry, if they can directly retrieve the onfile public key from the domain name trust root for authentication purposes ... then it is possible that others could also directly rely on the same domain name trust root (that the certification autorities are relying on)
a radically simplified ssl setup protocol could involve DNS requests (for domain name to ip-address translation) to piggy back (in the response) any available public key and any crypto options. then the client-to-server connection could have the client initially generating a random ssl session key, encrypting the data with the session key, and encrypting the session key with the (servers) public key. the server demonstrates that they have the corresponding private key by a correct encrypted response (eliminating all the ssl domain name certificate operations and all the ssl protocol setup chatter)
recent thread in some crypto mailing list discussing radically simplified
SSL based on using onfile public keys at the domain name infrastructure
https://www.garlic.com/~lynn/aadsm25.htm#17
https://www.garlic.com/~lynn/aadsm25.htm#19
https://www.garlic.com/~lynn/aadsm25.htm#22
w/o needing digital certificates ... misc. past posts mentioning
various public key operations w/o requiring digital certificates
... including real-time, onfile public key implementations:
https://www.garlic.com/~lynn/subpubkey.html#certless
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: SSL, Apache 2 and RSA key sizes Newsgroups: sci.crypt,comp.infosystems.www.servers.unix Date: Sun, 27 Aug 2006 10:56:57 -0600Anne & Lynn Wheeler writes:
shortly after the work this payment gateway and e-commerce work in the mid-90s ... we also got involved in the x9a10 financial standard working group. the primary purpose of the dominate use of ssl e-commerce is hiding account numbers ... since just having knowledge of the account number can enable fraudulent transactions.
the x9a10 financial standard working group had been given the requirement to preserve the integrity of the financial infrastructure for all retail payments (debit, credit, stored-value, internet, point-of-sale, etc ... i.e. ALL). we observed that account numbers were required in scores of business processes and even if the planet was buried under miles of crypto (used for hiding account numbers), it still wouldn't be enuf to prevent account number leakage (and the resulting account fraud).
so the resulting x9.59 financial standard protocol
https://www.garlic.com/~lynn/x959.html#x959
https://www.garlic.com/~lynn/subpubkey.html#x959
specified authenticating the transaction (on end-to-end basis) along
with a business rule that account numbers used in x9.59 transactions
couldn't be used in non-authenticated transactions. this was
countermeasure to account fraud replay attacks ... where simple
knowledge of the account number could result in fraudulent
transactions. past post discussing some of the issues of protecting
account number used in scores of business processes
https://www.garlic.com/~lynn/2001h.html#61
with countermeasure to fraudulent transactions based on simply knowing the account number ... it is no longer required to hide the account number (in order to prevent such fraudulent transactions).
so while the previous post
https://www.garlic.com/~lynn/2006p.html#7 SSL, Apache 2 and RSA key sizes
discusses a drastically simplified SSL protocol ... while x9.59 eliminates the requirement for the dominate use of SSL protocol for e-commerce purposes ... the hiding of account numbers as a countermeasure to fraudulent transactions (i.e. hiding the account number was no longer necessary as a countermeasure to account fraud).
somewhat related recent blog thread discussing issues of having
limited scope hiding paradigms as a countermeasure to account
fraud ... as opposed to strongly authenticated end-to-end transaction
authentication as a countermeasure to account fraud.
https://www.garlic.com/~lynn/aadsm24.htm#5 New ISO standard aims to ensure the security of financial transactions on the Internet
https://www.garlic.com/~lynn/aadsm24.htm#7 Naked Payments IV - let's all go naked
https://www.garlic.com/~lynn/aadsm24.htm#9 Naked Payments IV - let's all go naked
https://www.garlic.com/~lynn/aadsm24.htm#10 Naked Payments IV - let's all go naked
https://www.garlic.com/~lynn/aadsm24.htm#12 Naked Payments IV - let's all go naked
https://www.garlic.com/~lynn/aadsm24.htm#14 Naked Payments IV - let's all go naked
https://www.garlic.com/~lynn/aadsm24.htm#22 Naked Payments IV - let's all go naked
https://www.garlic.com/~lynn/aadsm24.htm#25 FraudWatch - Chip&Pin
https://www.garlic.com/~lynn/aadsm24.htm#26 Naked Payments IV - let's all go naked
https://www.garlic.com/~lynn/aadsm24.htm#41 Naked Payments IV - let's all go naked
https://www.garlic.com/~lynn/aadsm24.htm#42 Naked Payments II - uncovering alternates, merchants v. issuers
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: New airline security measures in Europe Newsgroups: bit.listserv.ibm-main Date: Sun, 27 Aug 2006 16:44:23 -0600Phil Payne wrote:
when we were doing ibm ha/cmp ... we considered a very wide variety of
threats ...
https://www.garlic.com/~lynn/subtopic.html#hacmp
there have been numerous studies ... even recently ... that the majority of fraud involve insiders ... it is just that the external attacks are much more likely to make the press.
then there is these recent news articles:
Secret Service: Inside Attacks Generally Launched By Problem Employees
http://www.informationweek.com/showArticle.jhtml?articleID=192300415
Study Highlights Insider Threats
http://www.informationweek.com/showArticle.jhtml?articleID=192300421
now, probably by definition, anybody responsible for an insider attack is likely to be labeled a problem employee.
an older post citing a study that up to seventy percent of ID thefts
involve an insider
https://www.garlic.com/~lynn/aadsm17.htm#38 Study: ID theft usually an inside job
lots of collected posting about threats, fraud, vulnerabilities, and risks
https://www.garlic.com/~lynn/subintegrity.html#fraud
misc. past posts specifically mentioning insider attacks:
https://www.garlic.com/~lynn/aadsm6.htm#terror8 [FYI] Did Encryption Empower These Terrorists?
https://www.garlic.com/~lynn/aadsm14.htm#4 Who's afraid of Mallory Wolf?
https://www.garlic.com/~lynn/aadsm16.htm#20 Ousourced Trust (was Re: Difference between TCPA-Hardware and a smart card and something else before
https://www.garlic.com/~lynn/aadsm17.htm#25 Single Identity. Was: PKI International Consortium
https://www.garlic.com/~lynn/aadsm18.htm#18 Any TLS server key compromises?
https://www.garlic.com/~lynn/aadsm24.htm#5 New ISO standard aims to ensure the security of financial transactions on the Internet
https://www.garlic.com/~lynn/aadsm24.htm#10 Naked Payments IV - let's all go naked
https://www.garlic.com/~lynn/2002e.html#18 Opinion on smartcard security requested
https://www.garlic.com/~lynn/2002j.html#14 Symmetric-Key Credit Card Protocol on Web Site
https://www.garlic.com/~lynn/2002j.html#40 Beginner question on Security
https://www.garlic.com/~lynn/2002m.html#46 Encryption algorithm for stored data
https://www.garlic.com/~lynn/2004f.html#31 MITM attacks
https://www.garlic.com/~lynn/2005i.html#1 Brit banks introduce delays on interbank xfers due to phishing boom
https://www.garlic.com/~lynn/2005k.html#1 More on garbage
https://www.garlic.com/~lynn/2005v.html#2 ABN Tape - Found
https://www.garlic.com/~lynn/2006k.html#16 Value of an old IBM PS/2 CL57 SX Laptop
https://www.garlic.com/~lynn/2006k.html#33 Password Complexity
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: What part of z/OS is the OS? Newsgroups: bit.listserv.ibm-main,alt.folklore.computers Date: Mon, 28 Aug 2006 12:54:27 -0600Alan Altmark writes:
in the transition to mvs ... all the different things outside of the kernel got their own virtual address space ... this made pointer passing paradigm somewhat problematical for services running in a different address space. common segment was the initial solution ... but for larger 168 mvs shops ... it wasn't unusual to find the mvs kernel taking up 8mbytes of every virtual address space (preserving the pointer passing paradigm between applications and real kernel services) and csa taking five megabytes (allowing pointer passing paradigm to work between applications and services in different virtual address spaces). this was starting to put significant constraint on some applications ... leaving only maximum of 3mbytes out of every application virtual address space ... for actual application use.
access registers then generalized the dual-address space support introduced in 3033.
a few posts this year mentioning common segment in support of
pointer passing paradigm
https://www.garlic.com/~lynn/2006b.html#25 Multiple address spaces
https://www.garlic.com/~lynn/2006b.html#28 Multiple address spaces
https://www.garlic.com/~lynn/2006b.html#32 Multiple address spaces
https://www.garlic.com/~lynn/2006i.html#33 virtual memory
https://www.garlic.com/~lynn/2006j.html#38 The Pankian Metaphor
https://www.garlic.com/~lynn/2006k.html#44 virtual memory
for a somewhat different take ... the vm370 had spool file operation
embedded in the kernel. as mentioned in recent posts:
https://www.garlic.com/~lynn/2006e.html#36 The Pankian Metaphor
https://www.garlic.com/~lynn/2006k.html#51 other cp/cms history
https://www.garlic.com/~lynn/2006o.html#64 The Fate of VM - was: Re: Baby MVS???
i was running into severe thruput bottleneck with the vm spool file
implementation in conjunction with the internal network
https://www.garlic.com/~lynn/subnetwork.html#internalnet
and our high-speed backbone (part of our hsdt project)
https://www.garlic.com/~lynn/subnetwork.html#hsdt
so my take was to take the majority of the vm kernel spool file function, move it to a service virtual machine, re-code it in vs/pascal and increase the thruput by an order of magnitude ... eliminating many of its thruput constraints.
one of the long term issues with virtual machine hypervisor was the original code (from cp67) was very small, compact, and consistent. the early philosophy was that unless it couldn't absolutely be done any other way ... it didn't belong in the kernel. It was a highly efficient micro-kernel. The downside was that for people with more of a traditional operating system background ... they found the concise, compact implementation easy to understand and modify. The result was a tendency to take the easy way out and add new feature/function into the kernel code itself.
frequently w/o stringently enforced microkernel standards ... the micro-kernel tended to become extremely bloated, starting to resemble the kernels of more traditionally implemented operating systems ... becoming more and more bloating and much more difficult to maintain and modify (the ease of modification somewhat leading to its own downfall).
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: What part of z/OS is the OS? Newsgroups: bit.listserv.ibm-main,alt.folklore.computers Date: Mon, 28 Aug 2006 13:44:13 -0600Anne & Lynn Wheeler wrote:
this brings to my mind somebody's line that goes something like "it isn't done when there is no more to add, it is done when there is no more to take away"
applied to micro-kernel efforts ... with somebody's related observation that maintaining a KISS implementation can actually be significantly more difficult than doing a complex implementation.
however, there is a corollary about KISS implementation being applicable
to the situation. recent posts mentioning how simple handling of FINWAIT
processing in tcp session close ... made some implicit assumptions about
the environment that were violated with HTTP use of TCP sessions.
https://www.garlic.com/~lynn/aadsm25.htm#17 Hamiltonian path as protecti on against DOS
https://www.garlic.com/~lynn/aadsm25.htm#19 Hamiltonian path as protection against DOS
the mention of the spool file system rewrite in the previous posts
https://www.garlic.com/~lynn/2006e.html#36 The Pankian Metaphor
https://www.garlic.com/~lynn/2006k.html#51 other cp/cms history
https://www.garlic.com/~lynn/2006o.html#64 The Fate of VM - was: Re: Baby MVS???
addressed a problem similar to what showed up with FINWAIT handling on heavily loaded webservers in the mid-90s. native vm spool processing had a linear list of all spool files ... and all spool file operations involved searching the linear list. this had non-linear increase in overhead as systems scaled. this is also similar to the original cp67 kernel storage management that used a single linear list ... before subpool logic was introduced to cp67 kernel in the early 70s.
in any case, my vs/pascal spool file rewrite introduced both a hash table and a tree structure for managing spool files.
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: sorting Newsgroups: alt.folklore.computers Date: Tue, 29 Aug 2006 07:47:41 -0600Anne & Lynn Wheeler writes:
Market Forces vs. Traffic Jams; New research shows that making drivers
pay higher tolls at peak times and tracking their location with RFID
or GPS technology can eliminate traffic jams.
http://www.technologyreview.com/read_article.aspx?id=17373&ch=infotech
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: What part of z/OS is the OS? Newsgroups: bit.listserv.ibm-main,alt.folklore.computers Date: Tue, 29 Aug 2006 09:26:20 -0600J R wrote:
in the past, kernels tended to refer to privilege/supervisor execution and protected storage. lots of kernels have implemented protected storage with virtual address spaces ... i.e. cp67 on 360/67. mvt used 360 storage protection.
as technology progressed there was a direction (like for fault isolation) to provide greater granularity for both privileges and storage protection/isolation.
so from a structuring standpoint, system services got a lot less distinct with much greater levels of privileges and storage isolation.
a couple months ago there was talk by one of the vendors about moving SSL processing into the kernel. the issue was that they were going to be supporting SSL crypto hardware accelerator devices. In order to provide support for potentially multiple different applications sharing a common device ... SSL processing (use of a shared device) became a resource and protection management issue (typical requirement for system services).
Discussion of some of the repercussions in the SSL security model that
were the result of the SSL crypto processing overhead ... as well as
some discussion as to how many of the requirements (that rely on SSL)
might be addressed in other ways:
https://www.garlic.com/~lynn/2006p.html#7 SSL, Apache 2 and RSA key sizes
https://www.garlic.com/~lynn/2006p.html#8 SSL, Apache 2 and RSA key sizes
in the referenced discussion (about moving SSL support into the kernel)
there was also mention of repeated efforts trying to get tcp/ip protocol
stack out of the kernel in the secure, capability coyotos secure
operating system
http://www.coyotos.org/
coyotos heritage is eros
http://www.eros-os.org/
http://www.capros.org/
the eros/capros heritage is keyKOS
http://cap-lore.com/CapTheory/upenn/
http://cap-lore.com/CapTheory/upenn/#keylogic
keykos is the renamed gnosis by the key logic spin-off of tymshare after
MD bought tymshare. gnosis was a secure 370-based operating system
developed by tymshare. tymshare happened to have been one of the early
cp67/vm370 commercial time-sharing offerings in the late 60s and 70s
https://www.garlic.com/~lynn/submain.html#timeshare
disclaimer, i was brought in to do gnosis audit and evaluation as part
of the gnosis spin-off for key logic. misc. past posts mentioning
gnosis or keykos
https://www.garlic.com/~lynn/2000f.html#69 TSS ancient history, was X86 ultimate CISC? designs)
https://www.garlic.com/~lynn/2000g.html#22 No more innovation? Get serious
https://www.garlic.com/~lynn/2001b.html#73 7090 vs. 7094 etc.
https://www.garlic.com/~lynn/2001g.html#33 Did AT&T offer Unix to Digital Equipment in the 70s?
https://www.garlic.com/~lynn/2001g.html#35 Did AT&T offer Unix to Digital Equipment in the 70s?
https://www.garlic.com/~lynn/2001n.html#10 TSS/360
https://www.garlic.com/~lynn/2002f.html#59 Blade architectures
https://www.garlic.com/~lynn/2002g.html#0 Blade architectures
https://www.garlic.com/~lynn/2002g.html#4 markup vs wysiwyg (was: Re: learning how to use a computer)
https://www.garlic.com/~lynn/2002h.html#43 IBM doing anything for 50th Anniv?
https://www.garlic.com/~lynn/2002i.html#63 Hercules and System/390 - do we need it?
https://www.garlic.com/~lynn/2002j.html#75 30th b'day
https://www.garlic.com/~lynn/2003g.html#18 Multiple layers of virtual address translation
https://www.garlic.com/~lynn/2003h.html#41 Segments, capabilities, buffer overrun attacks
https://www.garlic.com/~lynn/2003i.html#15 two pi, four phase, 370 clone
https://www.garlic.com/~lynn/2003k.html#50 Slashdot: O'Reilly On The Importance Of The Mainframe Heritage
https://www.garlic.com/~lynn/2003l.html#19 Secure OS Thoughts
https://www.garlic.com/~lynn/2003l.html#22 Secure OS Thoughts
https://www.garlic.com/~lynn/2003l.html#26 Secure OS Thoughts
https://www.garlic.com/~lynn/2003m.html#24 Intel iAPX 432
https://www.garlic.com/~lynn/2003m.html#54 Thoughts on Utility Computing?
https://www.garlic.com/~lynn/2004c.html#4 OS Partitioning and security
https://www.garlic.com/~lynn/2004e.html#27 NSF interest in Multics security
https://www.garlic.com/~lynn/2004m.html#29 Shipwrecks
https://www.garlic.com/~lynn/2004m.html#49 EAL5
https://www.garlic.com/~lynn/2004n.html#41 Multi-processor timing issue
https://www.garlic.com/~lynn/2004o.html#33 Integer types for 128-bit addressing
https://www.garlic.com/~lynn/2004p.html#23 Systems software versus applications software definitions
https://www.garlic.com/~lynn/2005.html#7 How do you say "gnus"?
https://www.garlic.com/~lynn/2005b.html#6 [Lit.] Buffer overruns
https://www.garlic.com/~lynn/2005b.html#7 [Lit.] Buffer overruns
https://www.garlic.com/~lynn/2005b.html#12 [Lit.] Buffer overruns
https://www.garlic.com/~lynn/2005c.html#67 intel's Vanderpool and virtualization in general
https://www.garlic.com/~lynn/2005d.html#43 Secure design
https://www.garlic.com/~lynn/2005d.html#50 Secure design
https://www.garlic.com/~lynn/2005h.html#13 Today's mainframe--anything to new?
https://www.garlic.com/~lynn/2005k.html#30 Public disclosure of discovered vulnerabilities
https://www.garlic.com/~lynn/2005s.html#12 Flat Query
https://www.garlic.com/~lynn/2006k.html#37 PDP-1
https://www.garlic.com/~lynn/2006m.html#34 PDP-1
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: Health Care Newsgroups: alt.folklore.computers Date: Tue, 29 Aug 2006 10:28:58 -0600re:
the gao has projections that ss, medicare and medicaid program spending grows to over 25percernt of GDP.
a recent news item on health care costs and medicare/medicaid program spending
Taxpayers' hospital tab takes turn for the worse
http://www.denverpost.com/business/ci_4234325
that medicare/medicaid programs paid for over half of colorado hospital patient days in 2005 (and numbers may be similar in other states).
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: "25th Anniversary of the Personal Computer" Newsgroups: alt.folklore.computers Date: Tue, 29 Aug 2006 17:22:18 -0600"William J. Leary Jr." writes:
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: Comic Sans was Re: An alternative history... Newsgroups: alt.folklore.computers Date: Wed, 30 Aug 2006 07:19:43 -0600Brian Inglis writes:
another invention brought to you courtesy of the science center, 4th
flr, 545 tech sq.
https://www.garlic.com/~lynn/subtopic.html#545tech
current w3c offices are just around the corner from 545 tech sq.
past postings mentioning waterloo "script", clone of cms "script"
(text formating implementing gml/sgml) in use at cern
https://www.garlic.com/~lynn/2004l.html#72 Specifying all biz rules in relational data
https://www.garlic.com/~lynn/2005.html#27 Network databases
https://www.garlic.com/~lynn/2005e.html#34 Thou shalt have no other gods before the ANSI C standard
https://www.garlic.com/~lynn/2006d.html#35 Fw: Tax chooses dead language - Austalia
https://www.garlic.com/~lynn/2006m.html#55 The System/360 Model 20 Wasn't As Bad As All That
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: Health Care Newsgroups: alt.folklore.computers Date: Wed, 30 Aug 2006 07:26:46 -0600jmfbahciv writes:
the referenced comptroller general talk makes references to using conservative numbers ... possibly assuming all "best case" scenarios that would be difficult to argue with?
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: 19,000 Accounts Compromised Newsgroups: bit.listserv.ibm-main Date: Wed, 30 Aug 2006 08:52:19 -0600allan.staller@ibm-main.lst (Staller, Allan) writes:
and of course the old standby posting ... security proportional to risk
https://www.garlic.com/~lynn/2001h.html#61
and a few other news URLs from this morning:
AT&T says hackers accessed customers' cards
http://news.yahoo.com/s/nm/20060829/tc_nm/telecoms_att_data_dc
AT&T says hackers accessed customers' credit cards
http://today.reuters.com/news/articlenews.aspx?type=technologyNews&storyID=2006-08-29T232958Z_01_WEN4690_RTRUKOC_0_US-TELECOMS-ATT-DATA.xml&WTmodLoc=NewsHome-C3-technologyNews-2
AT&T Offers Credit Monitoring Service to Customers Whose Credit Cards
Were Accessed
http://www.prnewswire.com/cgi-bin/stories.pl?ACCT=104&STORY=/www/story/08-29-2006/0004423795&EDATE=
Flurry of data breaches exposes personal data on thousands
http://www.computerworld.com/action/article.do?command=viewArticleBasic&taxonomyName=security&articleId=9002828&taxonomyId=17AMP;INTSRC=KC_TOP
AT&T hack exposes 19,000 identities
http://news.com.com/AT38T+hack+exposes+19%2C000+identities/2100-1029_3-6110765.html
Flurry of data breaches exposes personal data on thousands
http://www.computerworld.com/action/article.do?command=viewArticleBasic&articleId=9002828
Study: Many believe data thefts can't be prevented
http://www.computerworld.com/action/article.do?command=viewArticleBasic&taxonomyName=security&articleId=9002834&taxonomyId=17&intsrc=kc_top
Peering at Identity Fraud as Hackers Break into AT&T System
http://www.sda-asia.com/sda/features/psecom,id,559,nodeid,1,_language,Singapore.html
AT&T breach affects 19,000 customers
http://searchsecurity.techtarget.com/originalContent/0,289142,sid14_gci1213279,00.html
AT&T Breached, Exposes 19,000 Identities
http://it.slashdot.org/it/06/08/30/0332220.shtml
AT&T says hackers accessed customers' cards
http://news.yahoo.com/s/nm/telecoms_att_data_dc
AT T Cracked For Credit Cards
http://www.securitypronews.com/insiderreports/insider/spn-49-20060830ATTCrackedForCreditCards.html
Credit card fraud causes cancellation of over 1,000 Barbra Streisand
show tickets
http://www.earthtimes.org/articles/show/8434.html
Thousands exposed by AT&T hack
http://news.zdnet.co.uk/internet/security/0,39020375,39282020,00.htm
Hackers break into AT&T's online store
http://software.silicon.com/security/0,39024655,39161840,00.htm
AT&T Web Store Hacked, Up to 19K Affected
http://www2.csoonline.com/blog_view.html?CID=24366
AT&T Says Hackers Accessed Customers' Cards
http://www.informationweek.com/news/showArticle.jhtml?articleID=192500234
AT&T online store hacked, data compromised
http://www.infoworld.com/article/06/08/30/HNat&tstorehacked_1.html
AT&T says hackers accessed customers' credit cards
http://www.computerworld.com/action/article.do?command=viewArticleBasic&articleId=9002843
Hackers Hit AT&T System, Get Credit Card Info
http://www.eweek.com/article2/0,1895,2010001,00.asp
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: What part of z/OS is the OS? Newsgroups: bit.listserv.ibm-main,alt.folklore.computers Date: Wed, 30 Aug 2006 09:06:53 -0600Craig.Mullins@ibm-main.lst (Craig Mullins) writes:
... from recent posting
https://www.garlic.com/~lynn/2006p.html#15 "25th Anniversary of the Personal Computer"
involving some copies of old email from long ago and far away ...
one of the items mentioned was 2 chip operating system processor:
Date: 29 September 1982, 10:46:37 EST
To: wheeler
Hm, interesting article you sent....
I obtained advance information about the Intel iAPX286 .... it looks
very interesting.... also have some data on the iAPX 86/30 and 88/30
Operating system processors.... this looks extremely interesting, and
one can assume that the 286 cannot be far behind in getting an
operating system chip to go with it....
iAPX86/30 is a 2 chip processor, with 35 operating system processor
primitives as instructions... things like job and task management,
interrupt management, free memory management, intertask communication,
intertask synchronization, and environmental control... It also
supports 5 operating system data types: jobs, tasks, segments,
mailboxes, and regions. Someday we'll be able to look back at the big
RISC vs. CISC and wonder what all the fuss was about....
... snip ... top of post, old email index
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: news group maintenance: SPEC CPU2006 announced Newsgroups: comp.arch Date: Wed, 30 Aug 2006 09:35:48 -0600Del Cecchi writes:
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: SAT Reading and Math Scores Show Decline Newsgroups: alt.folklore.computers Date: Wed, 30 Aug 2006 10:40:16 -0600SAT Reading and Math Scores Show Decline
misc. past related threads:
https://www.garlic.com/~lynn/2002k.html#41 How will current AI/robot stories play when AIs are real?
https://www.garlic.com/~lynn/2002k.html#45 How will current AI/robot stories play when AIs are real?
https://www.garlic.com/~lynn/2003b.html#45 hyperblock drift, was filesystem structure (long warning)
https://www.garlic.com/~lynn/2003i.html#28 Offshore IT
https://www.garlic.com/~lynn/2004b.html#38 The SOB that helped IT jobs move to India is dead!
https://www.garlic.com/~lynn/2004j.html#40 Many engineers lack even a four-year degree
https://www.garlic.com/~lynn/2005e.html#48 Mozilla v Firefox
https://www.garlic.com/~lynn/2005g.html#5 Where should the type information be?
https://www.garlic.com/~lynn/2005g.html#43 Academic priorities
https://www.garlic.com/~lynn/2006e.html#17 X.509 and ssh
https://www.garlic.com/~lynn/2006l.html#63 DEC's Hudson fab
https://www.garlic.com/~lynn/2006m.html#12 DEC's Hudson fab
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: Admired designs / designs to study Newsgroups: comp.arch Date: Wed, 30 Aug 2006 12:59:00 -0600eugene@cse.ucsc.edu (Eugene Miya) writes:
ssup/unix had been done for internal at&t
a few past posts mentioning tss370/ssup
https://www.garlic.com/~lynn/2004q.html#37 A Glimpse into PC Development Philosophy
https://www.garlic.com/~lynn/2005b.html#13 Relocating application architecture and compiler support
https://www.garlic.com/~lynn/2005c.html#20 [Lit.] Buffer overruns
https://www.garlic.com/~lynn/2005d.html#61 Virtual Machine Hardware
https://www.garlic.com/~lynn/2005s.html#34 Power5 and Cell, new issue of IBM Journal of R&D
https://www.garlic.com/~lynn/2006f.html#26 Old PCs--environmental hazard
https://www.garlic.com/~lynn/2006g.html#2 The Pankian Metaphor
https://www.garlic.com/~lynn/2006m.html#30 Old Hashing Routine
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: SAT Reading and Math Scores Show Decline Newsgroups: alt.folklore.computers Date: Wed, 30 Aug 2006 13:05:51 -0600Al Balmer writes:
but all the changes that i've heard that went on over the past 30 years always involved making the tests easier ... not harder.
i've commented before about doing some work with large mid-western state univ. ten years ago ... at the time, they had mentioned that they had dumbed down the entering freshman curriculum three times between the late 60s and the early 90s.
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: SAT Reading and Math Scores Show Decline Newsgroups: alt.folklore.computers Date: Wed, 30 Aug 2006 14:37:40 -0600kkt writes:
the first item returned
http://www.uwgb.edu/dutchs/PSEUDOSC/DENYSAT.HTM
... from above ...
National score data for the SAT are first available for 1952. Between
then and 1963, SAT test scores held constant or even increased,
despite the fact that the proportion of high-school students taking
the SAT rose from 7% in 1952 to 30% in 1963, and thus that many
less-qualified students were taking the test. It seems reasonable to
conclude that the quality of American education held steady or even
increased a bit during those years. In 1964, scores declined, and by
1970, national average scores on the verbal aptitude portion of the
SAT had fallen from 478 out of a possible 800 to 460; mathematical
aptitude scores fell from 502 to 488. When millions of people are
taking the test, even a small variation in the average can be
significant. By 1977, verbal scores were down to 429, math scores to
470. By 1981, scores had declined for 19 consecutive years; verbal
scores had fallen a total of 54 points to 424, math scores had fallen
36 points to 466. In 1982, for the first time in two decades, scores
rose; math by one point, verbal scores by two.
... snip ...
the above goes on to look at some studies correlating sat scores with
other factors:
The usual statistical measure of correlation is called the
"correlation coefficient". It has a value of 1 for perfect
correlation, zero for no correlation at all, and -1 for perfect
negative correlation. The correlation coefficient between SAT scores
and first-year college grades is 0.35. This is a rather moderate
correlation; it would be more useful to examine the correlation
between math SAT scores and mathematics grades, and so on. The Nader
Group prefers a different measure, the "percentage of perfect
prediction", which is the square of the correlation coefficient; in
this case 0.119, which is impressively smaller than 0.35. On this
basis, Nairn and Associates claim that the SAT scores account for only
11.9% of perfect prediction of first-year college grades and are
essentially worthless.
Now, what's the correlation coefficient between social class and SAT
score? Here Nairn and Associates pursue a very different
course. Unlike the correlation between test scores and grades, for the
link between family income and test scores they provide lengthy tables
comparing test scores and average family income. There is indeed a
correlation, but without the correlation coefficient, we have no way
of knowing how significant the correlation is -- and there is no
mention of the correlation coefficient anywhere in the discussion!
There is a passing reference to it in a footnote in the back of the
book; it is -- 0.35! The level of correlation that supposedly makes
tests worthless in predicting grades suddenly becomes ironclad proof
that social class determines test scores!
... snip ...
the following gives sat scores from school years 66-67 thru 04-05
http://nces.ed.gov/programs/digest/d05/tables/dt05_127.asp
minor extract ... the full table gives "old scale" scores for 66-95. it gives "new scale"(?) scores for 66-05 (the old scale having been "adjusted"?) ... the following is "new scale"(?) extract:
| Verbal score | Mathematics score| |__________________|__________________| School year|Total| Male|Female|Total| Male|Female| ___________|_____|_____|______|_____|_____|______| 1966-67 ...| 543| 540| 545| 516| 535| 495| 2003-04 ...| 508| 512| 504| 518| 537| 501| 2004-05 ...| 508| 513| 505| 520| 538 504|
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: SAT Reading and Math Scores Show Decline Newsgroups: alt.folklore.computers Date: Wed, 30 Aug 2006 16:31:18 -0600Al Balmer writes:
referenced several previous posts mentioning some aspects of the subject.
a few of the previously mentioned posts including references to
https://web.archive.org/web/20100413134230/http://www.nifl.gov/nifl/facts/facts_overview.html
and extracts from the 2003, National Assessment of Adult Literacy
for instance one such mentioned post was:
https://www.garlic.com/~lynn/2004b.html#42
which included some camparisions to other "high-income countries" (US ranking ranging between 14 and 19 out of 19).
and the SAT verbal score (i.e. non-math, more related to reading and
literacy) in this post
https://www.garlic.com/~lynn/2006p.html#24 Sat Reading and Match Scores Show Decline
from:
http://nces.ed.gov/programs/digest/d05/tables/dt05_127.asp
shows decline from 543 in the 66-67 school year to 499 in the 92-93 school years ... and then climbed back up to 508 in the 03-04 school year where it stayed for the 04-05 school year.
so the cited article
http://www.nytimes.com/2006/08/30/education/30sat.html?ex=1157601600&en=b251a151ba57e85b&ei=5040&partner=MOREOVERNEWS
says that the avg. score fell five points from 508 to 503.
note from the referenced table
http://nces.ed.gov/programs/digest/d05/tables/dt05_127.asp
there was also a five point increase between 93-94 (499) and 94-95 (504), a two point drop between 00-01 (506) to 01-02 (504) and a three point gain between 01-02 (504) to 02-03 (507).
after a relative rapid ten percent score drop over ten year period (from 66-67 school year) ... there had been a year-to-year one percent or less fluctuation (hitting a low of 499 in the 90-91 and 93-94 school years and a high of 508 in the 03-04 and 04-05 school years).
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: Admired designs / designs to study Newsgroups: comp.arch Date: Wed, 30 Aug 2006 16:46:06 -0600eugene@cse.ucsc.edu (Eugene Miya) writes:
there was something of a chicken and egg scenario that the prices were so high because the forecast was so small and the forecast was so small because the price was so high.
actually they started out saying that they weren't going to allow mainframe tcp/ip products at all ... and then they fell back to the position that the only market for mainframe tcp/ip products were the maximum 14 projected tss/370 unix installations.
somewhat related ... the eventual box sold was crippled in other ways
(besides the price). it was eventually sold to other than tss/370 unix
installations running other mainframe operating systems ... typical
operation got 44mbyte/sec sustained thruput burning a 3090 processor.
misc. past posts implementing rfc 1044 support and some testing at
cray research getting 1mbyte sustained thruput
https://www.garlic.com/~lynn/subnetwork.html#1044
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: What part of z/OS is the OS? Newsgroups: bit.listserv.ibm-main,alt.folklore.computers Date: Wed, 30 Aug 2006 17:36:16 -0600Alan_Altmark@ibm-main.lst (Alan Altmark) writes:
among other things, stu implemented cms script ... that supported
"dot" formating commands (similar to runoff). later, at the science
center, "G", "M", and "L" invented gml ... and gml tag processing was
added to script (for quite awhile you could find gml tags intermixed
with "dot" formating controls in script documents).
https://www.garlic.com/~lynn/submain.html#sgml
old post mentioning document formating history
https://www.garlic.com/~lynn/2003o.html#32 who invented the "popup" ?
PDP-1 Expensive Typewriter (Peter Sampson) about 1962
CTSS RUNOFF (Jerry Saltzer) 1964-65
CMS SCRIPT (Stuart E. Madnick) 1967
CTSS BCPL runoff (Rudd Canaday, Dennis Ritchie) 1967-68
Multics BCPL runoff (Canaday, Ritchie, Ossanna) 1968
UNIX troff (J. F. Ossanna) dunno
...
misc other past posts mentioning madnick
https://www.garlic.com/~lynn/99.html#91 Documentation query
https://www.garlic.com/~lynn/2000e.html#0 What good and old text formatter are there ?
https://www.garlic.com/~lynn/2001b.html#50 IBM 705 computer manual
https://www.garlic.com/~lynn/2001g.html#54 DSRunoff; was Re: TECO Critique
https://www.garlic.com/~lynn/2002b.html#46 ... the need for a Museum of Computer Software
https://www.garlic.com/~lynn/2002g.html#67 Coulda, Woulda, Shoudda moments?
https://www.garlic.com/~lynn/2004l.html#73 Specifying all biz rules in relational data
https://www.garlic.com/~lynn/2004l.html#74 Specifying all biz rules in relational data
https://www.garlic.com/~lynn/2005e.html#34 Thou shalt have no other gods before the ANSI C standard
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: Greatest Software Ever Written? Newsgroups: alt.folklore.computers Date: Wed, 30 Aug 2006 18:31:51 -0600"Mickey" writes:
another rexx historical reference (gone 404, but lives on at wayback machine):
https://web.archive.org/web/20050309184016/http://www.computinghistorymuseum.org/ieee/af_forum/read.cfm?forum=10&id=21&thread=7
object rexx was created in 1997 ...and now available
http://www.oorexx.org/
http://www.oorexx.org/products.html
my misc. past postings about doing "dumprx" in rex ... wanting
to demonstrate that rex wasn't just another pretty scripting
language (like EXEC and EXEC2)
https://www.garlic.com/~lynn/submain.html#dumprx
a much simpler rex program i wrote in 80 ... from long ago and far away:
/* supply list of biggest pigs of CP spool system */
hi='1de8'x; lo='1d60'x; /* Bright up/down */
'DEPTH'
if rc<=1 then do
hi=' '; lo=' '; end
else 'CLEAR'
arg na; if na ^='' then do
if datatype(na) ^= 'NUM' then signal tell
end
else na = 19;
db=0
if db then say time() 'at entry'
parse value cpa('CPR QUERY FILES') with 'FILES:' rdr ' RDR, ' prt ' PRT, ' pun ' PUN'
rdr=strip(rdr,'B')
prt=strip(prt,'B')
pun=strip(pun,'B')
if rdr = 'NO' then rdr = 0
if prt = 'NO' then prt = 0
if pun = 'NO' then pun = 0
rdr = rdr + 0; prt = prt + 0; pun = pun + 0;
ku=0; kf = 0; kr = 0; sw = 0;
qcls = 'PUN'
call Qrdr
if rln ^> pun then sw = sw + 1
if db then say time() rln 'pun'
qcls = 'PRT'
call Qrdr
if rln ^> prt then sw = sw + 1
if db then say time() rln 'prt'
qcls = 'RDR'
call Qrdr
if rln ^> rdr then sw = sw + 1
if db then say time() rln 'rdr'
if sw ^= 0 then signal xx
yy:
'MAKEBUF'
kuk = 0
do i=1 to ku
name = nar.i
if k.name > 0 then do
queue right(k.name,8) || ' ' || name || ' ' || f.name
kuk = kuk + 1
end
end
queue
'TSORT 1 8 (REVERSE'
do i=1 to kuk
if i > na then leave
pull recs name files
if recs < 100 then leave
say left(name,9) || right(files,4) || ' files ' || right(recs,7) || ' records'
end
'DESBUF'
say 'total: ' || hi || right(kf,4) || lo || 'files' || hi || right(kr,7) || lo || 'records'
tot = rdr + prt + pun
say 'FILES: ' || right(tot,5) || ' tot, ' || right(rdr,4) || ' rdr, ' || right(prt,4) || ' prt, ' || right(pun,4) || ' pun'
exit
Qrdr:
parse value cpa('CP QUERY' qcls) with . . . . rln .
if rln < 2 then return
parse value cpa('R') with owner . /* check header line */
if owner = 'OWNERID' then ss = 1
else ss = 0
do rl=2 to rln
parse value cpa('R') with name fnum clas type records rest
if datatype(records)^='NUM' then do
say 'Arrgh! records var "'records'" not numeric in:'
say name fnum clas type records rest
say 'name' name 'fnum' fnum 'clas' clas 'type' type
iterate rl
end
if type='DMP' then records=records*50 /* for CP dumps each is a whole page*/
else records=(records+49)%50*50 /* round to nearest page assuming cards */
if records=0 then do
say 'Erk! Recs=0?' name fnum clas type records rest
end
if s.name ^= 0 then do
ku = ku + 1
nar.ku = name
s.name = 0
f.name = 0
k.name = 0
end
if ss = 1 then do
f.name = f.name + 1
kf = kf + 1
k.name = k.name + records
kr = kr + records
end
end
return
xx:
if db then say 'xx routine entered'
qcls = ' RDR * '
call Qrdr
do i = 1 to 26
z = substr('ABCDEFGHIJKLMNOPQRSTUVWXYZ',I,1)
qcls = ' RDR CL ' || z
call Qrdr
end
kf = 0; kr = 0;
do j=1 to ku
name = nar.j
f.name = 0; k.name = 0;
qcls = ' RDR ' || nar.j
call Qnamx
qcls = ' PRT ' || nar.j
call Qnamx
qcls = ' PUN ' || nar.j
call Qnamx
end
signal yy
Qnamx:
x=cpa('CP QUERY ' || qcls); parse var x . . . . rln .
do rl=1 to rln
x=cpa('R') /* read next line from Q N response */
parse var x garb fnum clas type records rest
if datatype(records) ^= 'NUM' then iterate
if s.garb ^= 0 then do
ku = ku + 1
nar.ku = garb
s.garb = 0
end
f.name = f.name + 1
k.name = k.name + records
kf = kf + 1; kr = kr + records
end
return
--------
Tell:
parse source . . . . . me .
say ' ' me ' < no. > '
say 'displays number of spool files and records allocated by user'
say '(sorted by no. records). Top 19 users (or number specified)'
say 'are displayed.'
exit 100
/* Lynn Wheeler */
/* November 80 */
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: Greatest Software Ever Written? Newsgroups: alt.folklore.computers Date: Wed, 30 Aug 2006 20:26:44 -0600Brian Inglis writes:
earliest record that i have to hartmann and cms pipes is in 87 ... 6-7 years after the posted rex example.
earliest customer reference is end of 88 ... from vmshare archives:
http://vm.marist.edu/~vmshare/browse.cgi?fn=PIPELINE&ft=MEMO
leading up to that, john had done other things like toy ... contribution
for John's 50th b'day
https://www.garlic.com/~lynn/96.html#4a John Hartmann's Birthday Party
the above contains abstract of talk John gave at a conference I held mar82.
John's 50th b'day web pages
http://vm.marist.edu/~piper/party/jph-01.html
a few other posts mentioning john
https://www.garlic.com/~lynn/2002o.html#33 Over-the-shoulder effect
https://www.garlic.com/~lynn/2004d.html#39 System/360 40th Anniversary
old email from john
Date: 07/17/78 17:22:00
To: wheeler
Hi, Lynn. Howi is life in sunny California? I have bben studying the
SEPP scheduler a bit to figure out how the various things are computed
etc. Rich Kogut said that no-one can understand all of it (maybe
except for you) and I tend to agree with him. If you can, please
explain about
1. Around statement 301600 the guy who gets compute bound is inserted
in the runlist based on a recomputed priority, but VMEPRIOR is re-set
to the original priority after he has been inserted. Why does the
priority not correspond to where he is in the list? It must screw up
the addlist routine.
2. The working set calculation is based on the calculation of max
resident pages * max+1 (which is pages squared) which is subtracted
from the sum of resident pages at read plus the currently resident
pages (I cant decide what the unit of this is: pages times page reads,
I think). This is like comparing apples and pears (isnt it). What is
the reasoning behind this. Around line 713100.
3. Calculating the delay based on the external user priority certainly
keeps the high speed multiply on a 168 busy, but why was it not made
as a table look-up? Lines 740100.
Thanks a lot. John Hartmann 17JUL78 17:36 CET.
... snip ... top of post, old email index
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: Greatest Software Ever Written? Newsgroups: alt.folklore.computers Date: Wed, 30 Aug 2006 20:35:48 -0600Anne & Lynn Wheeler writes:
ref
https://www.garlic.com/~lynn/2006p.html#28 Greatest Software Ever Written?
https://www.garlic.com/~lynn/2006p.html#27 Greatest Software Ever Written?
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: "25th Anniversary of the Personal Computer" Newsgroups: alt.folklore.computers Date: Thu, 31 Aug 2006 08:13:56 -0600"Jukka Aho" writes:
we had been doing terminal emulation scripting using mainframe virtual
terminal facility ... earlier with parasite/story ... first showed up
about the same time as the early rex ...
https://www.garlic.com/~lynn/2006p.html#28 Greatest Software Ever Written
some of the syntax was similar to rex ... but was completely different.
old parasite/story terminal scripting ... a few old parasite/story
postings:
https://www.garlic.com/~lynn/2001k.html#35 Newbie TOPS-10 7.03 question
https://www.garlic.com/~lynn/2003i.html#73 Computer resources, past, present, and future
https://www.garlic.com/~lynn/2003j.html#24 Red Phosphor Terminal?
https://www.garlic.com/~lynn/2004e.html#14 were dumb terminals actually so dumb???
https://www.garlic.com/~lynn/2005r.html#12 Intel strikes back with a parallel x86 design
https://www.garlic.com/~lynn/2006.html#3 PVM protocol documentation found
https://www.garlic.com/~lynn/2006c.html#14 Program execution speed
https://www.garlic.com/~lynn/2006f.html#37 Over my head in a JES exit
https://www.garlic.com/~lynn/2006m.html#35 Draft Command Script Processing Manual
https://www.garlic.com/~lynn/2006n.html#23 sorting was: The System/360 Model 20 Wasn't As Bad As All That
for some time, there was period that view the components of 3-tier as
independent ... this post mentioning project vis-a-vis personal
computers ... as alternatives. there is such a discussion in this
report about bell labs from the early 80s
https://www.garlic.com/~lynn/2006n.html#56 AT&T Labs vs. Google Labs - R&D History
from recent thread:
https://www.garlic.com/~lynn/2006p.html#28 Greatest Software Ever Written?
one of the rex historical references (gone 404 but lives on at wayback machine)
https://web.archive.org/web/20050309184016/http://www.computinghistorymuseum.org/ieee/af_forum/read.cfm?forum=10&id=21&thread=7
from above:
By far the most important influence on the development of Rexx was the
availability of the IBM electronic network, called VNET. In 1979, more
than three hundred of IBM's mainframe computers, mostly running the
Virtual Machine/370 (VM) operating system, were linked by VNET. This
store-and-forward network allowed very rapid exchange of messages
(chat) and e-mail, and reliable distribution of software. It made it
possible to design, develop, and distribute Rexx and its first
implementation from one country (the UK) even though most of its users
were five to eight time zones distant, in the USA.
... snip ...
i.e. and i've periodically noted that the internal network
https://www.garlic.com/~lynn/subnetwork.html#internalnet
had nearly 1000 nodes
https://www.garlic.com/~lynn/internet.htm#22
https://www.garlic.com/~lynn/2006k.html#3 Arpa address
compared to possibly 250 nodes at the great arpanet/internet switch
from arapnet to internworking protocol on 1/1/83
https://www.garlic.com/~lynn/2006k.html#40 Arpa address
the attached email references some evolution of 2-tier operation
... just between "mainframes" ... i.e. typical glass house operation
... like HONE that had been providing world wide online interactive
support to all field, marketing, and sales
https://www.garlic.com/~lynn/subtopic.html#hone
... and the "project" or "departmental" 43xx machines that were
starting to find their way into the branch offices.
Date: 07/06/81 14:50:37
To: wheeler
Hi Lynn,
I've just return from 10 glorious weeks in New York. I had the
privilege of attending SRI. Now that I'm back in the trenches I am
trying to get caught up on what's been happening in the real
world. How did your HyperChannel setup work out? Seems to me that it
could be a possible solution for a project I'm working on. If you have
a few minutes give me a call or send a message with your ideas to the
following:
We are trying to provide central maintenance for VM and VSE to the
Customer Support Centers located in about 150 branch offices. Initially
I have convinced 14 to work with me to develop the methodology to do so.
The CSCs have 4331 Model Group 2 with 4 meg and will run a VM/VSE
environment most of the time if not always. Central maintenence will
involve problem determination, PTF application, and component distribution.
The base systems will be generated here and distributed on tape but
looking to the future we expect to provide electronic distribution.
My biggest concern is what facility to use for bulk data communications.
So far I have agreement from Tampa to use the 56KB SNA backbone, and
from SBS to use an undetermined bandwidth (all the cities I selected
will have earth stations in the near future). Initially I will use
existing 9600 bps lines. If I use conventional TP, I am limited to
56KB due to the 4331 ICA. If I can sell something like the HyperChannel
I could take advantage of the satillite's higher speed (cost will be
a definite issue).
In any case your ideas will be appreciated. If you think it would be
beneficial to get together I can arrange that too. Be talking to you.
... snip ... top of post, old email index, HSDT email
part of the reference in the above is that HSDT (high-speed data
transport) project activity had already started ... using initially
terrestrial T1 (and non-sna protocol) ... and then adding satellite T1
links (for a while, hsdt even had its own dedicated transponder on
sbs4)
https://www.garlic.com/~lynn/subnetwork.html#hsdt
we even got to be VIPs at the 41D launch for SBS4
http://www.nasa.gov/mission_pages/shuttle/shuttlemissions/archives/sts-41D.html
http://science.ksc.nasa.gov/shuttle/missions/41-d/mission-41-d.html
http://science.ksc.nasa.gov/shuttle/missions/41-d/41-d-info.html
so what we started to see progressing (somewhat in parallel) was the proliferation of 2-tier operation between glass house and department/project computers ... and the evolution of terminal emulation PC operation into 2-tier (and client/server) operation.
the proliferation of these two, somewhat independent (2-tier) activities
started to then to evolve and coalesce into early, internal 3-tier
operations.
https://www.garlic.com/~lynn/subnetwork.html#3tier
however, by the time we were starting to make marketing presentations to customer executives on 3-tier ... the SAA effort was moving into full swing ... somewhat directed at trying to contain 2-tier, client/server ... and protect the existing terminal emulation install base as long as possible.
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: OT - hand-held security Newsgroups: bit.listserv.ibm-main,alt.folklore.computers Date: Thu, 31 Aug 2006 11:03:01 -0600Alan_Altmark@ibm-main.lst (Alan Altmark) writes:
are something you know authentication ... out of the 3-factor
authentication model
https://www.garlic.com/~lynn/subintegrity.html#3factor
some number of the tokens are something you have authentication ... but they also use some sort of "secret" to "prove" the possession of a unique object.
the issue in the "secret" paradigms ... is that the threat models
involves leakage of the secret (especially when it is stored and used
in so many places) and cross-domain exploits ... i.e. passwords and/or
secret-based tokens require a unique value for every security domain
... as a countermeasure to entities in one domain attacking another
domain, a form of insider attack as opposed to various outsider
attacks skimming/harvesting secret.
https://www.garlic.com/~lynn/subintegrity.html#harvest
part of the requirement for frequent secret changes is that secrets can leak (guessing, skimming, evesdropping, harvesting) w/o the entities being aware .. and then authentication replay attacks. this can happen with some forms of tokens (like magstripe), which may also be susceptible to evesdropping, skimming, harvesting attacks and the creation of counterfeit token for replay attacks. The issue of a purely something you have token, the person can notice a lost/stolen compromise and report it. However, a guessing, skimming, evesdropping, harvesting compromise might occur w/o the person being aware of it happening.
for cross-domain exploit and other reasons, there has also been a instititional-centric paradigm for hardware tokens ... i.e. each institution issues their own hardware tokens. I've frequently commented that if this were to ever take off ... you then would have one hardware token for every pin/password (which is scores or even on the order of hundred for some people).
I've periodically drawn the analogy with the mid-80s use of unique floppy disks as a DRM paradigm for applications programs ... i.e. appearance of hard disks was evolving installation of applications. There was early use of specially coded floppy disks as a DRM countermeasure to software pirating. If this paradigm ever had a large uptake ... there could be computers with hundreds of associated unique floppy disks (one per application) that the person would have to continually shuffle as they switched between applications. In the case of emerging token use, having a hundred or so tokens stuffed into a (very large) pocket.
As an aside, about the time of the ibm/pc announcement there were some investigation into adding a unique serial number chip to each motherboard and a software licensing paradigm ... similar to mainframe, based on storing the cpu identifier.
there are two-factor authentication schemes using both a pin/password (something you know) and a token (something you have), as a countermeasure to lost/stolen token. the issue here is an assumption that the multiple factors are subject to independent vulnerabilities. however, you find some of the pin/magstripe implementations being vulnerable to a common skimming compromise (i.e. both the magstripe and pin is recorded at the same), invalidating the assumption about independent vulnerabilities.
a similar infrastructure problem showed up with the two-factor
chip&pin deployments (with pin as countermeasure to
lost/stolen token). the chip would present some static data
authentication (as proof of having the unique something you
have) and then the infrastructure would ask the token if the
correct pin was entered. the attackers would skim the static data (in
much the same way that magstripes are being skimmed) and use it to
produce a counterfeit yes card. once the static data had been
checked by the infrastructure, the chip would be asked some number of
additional questions about business processes (like whether the
correct pin was entered) ... and, of course, the counterfeit yes
card would always answer YES (from where the exploit got
its name).
https://www.garlic.com/~lynn/aadsm22.htm#29 Meccano Trojans coming to a desktop near you
https://www.garlic.com/~lynn/aadsm24.htm#29 DDA cards may address the UK Chip&Pin woes
https://www.garlic.com/~lynn/aadsm24.htm#32 DDA cards may address the UK Chip&Pin woes
https://www.garlic.com/~lynn/aadsm25.htm#4 Crypto to defend chip IP: snake oil or good idea?
Again there wasn't an independent vulnerbility for the PIN entry ... and independent exploit assumptions regarding multi-factor authentication was no longer valid.
a few past posts discussing enabling token person-centric
infrastructure as an alternative to institution-centric infrastructure
https://www.garlic.com/~lynn/aadsm24.htm#49 Crypto to defend chip IP: snake oil or good idea?
https://www.garlic.com/~lynn/aadsm24.htm#52 Crypto to defend chip IP: snake oil or good idea?
https://www.garlic.com/~lynn/aadsm25.htm#7 Crypto to defend chip IP: snake oil or good idea?
https://www.garlic.com/~lynn/2005g.html#47 Maximum RAM and ROM for smartcards
https://www.garlic.com/~lynn/2005g.html#57 Security via hardware?
https://www.garlic.com/~lynn/2005m.html#37 public key authentication
https://www.garlic.com/~lynn/2005p.html#6 Innovative password security
https://www.garlic.com/~lynn/2005p.html#25 Hi-tech no panacea for ID theft woes
https://www.garlic.com/~lynn/2005t.html#28 RSA SecurID product
https://www.garlic.com/~lynn/2005u.html#26 RSA SecurID product
https://www.garlic.com/~lynn/2006d.html#41 Caller ID "spoofing"
https://www.garlic.com/~lynn/2006o.html#20 Gen 2 EPC Protocol Approved as ISO 18000-6C
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: SAT Reading and Math Scores Show Decline Newsgroups: alt.folklore.computers Date: Thu, 31 Aug 2006 11:19:35 -0600kkt writes:
thread reference:
https://www.garlic.com/~lynn/2006p.html#21 SAT Reading and Math Scores Show Decline
https://www.garlic.com/~lynn/2006p.html#23 SAT Reading and Math Scores Show Decline
https://www.garlic.com/~lynn/2006p.html#24 SAT Reading and Math Scores Show Decline
https://www.garlic.com/~lynn/2006p.html#25 SAT Reading and Math Scores Show Decline
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: "25th Anniversary of the Personal Computer" Newsgroups: alt.folklore.computers Date: Thu, 31 Aug 2006 13:20:28 -0600appended is another project/departmental reference from the early 80s ... similar to the 150 4331s for US branch offices mentioned in (from long ago and far away)
this is for european branch offices and is referred to as BOIS ... involving 4341s in EMEA (europe, middle east, and africa) branch offices.
the bois/ddp represents another emerging 2-tier paradigm with project/departmental computers moving out into the branch offices (but operated, supported, maintained, and interconnected into old style glass house operation).
some of the services were an adjunct to HONE ... the internal world-wide online interactive system for field, sales, and marketing started in the early 70s with cp67/cms systems.
a few other past posts mentioning departmental and/or distributed
computer stuff
https://www.garlic.com/~lynn/2001m.html#15 departmental servers
https://www.garlic.com/~lynn/2001n.html#23 Alpha vs. Itanic: facts vs. FUD
https://www.garlic.com/~lynn/2002.html#2 The demise of compaq
https://www.garlic.com/~lynn/2002.html#7 The demise of compaq
https://www.garlic.com/~lynn/2002d.html#4 IBM Mainframe at home
https://www.garlic.com/~lynn/2002h.html#52 Bettman Archive in Trouble
https://www.garlic.com/~lynn/2002i.html#30 CDC6600 - just how powerful a machine was it?
https://www.garlic.com/~lynn/2002j.html#4 HONE, ****, misc
https://www.garlic.com/~lynn/2003d.html#64 IBM was: VAX again: unix
https://www.garlic.com/~lynn/2003n.html#46 What makes a mainframe a mainframe?
https://www.garlic.com/~lynn/2003o.html#24 Tools -vs- Utility
https://www.garlic.com/~lynn/2004.html#46 DE-skilling was Re: ServerPak Install via QuickLoad Product
https://www.garlic.com/~lynn/2004j.html#57 Monster(ous) sig (was Re: Vintage computers are better
https://www.garlic.com/~lynn/2004k.html#23 US fiscal policy (Was: Bob Bemer, Computer Pioneer,Father of
https://www.garlic.com/~lynn/2004q.html#71 will there every be another commerically signficant new ISA?
https://www.garlic.com/~lynn/2005d.html#49 Secure design
https://www.garlic.com/~lynn/2005m.html#12 IBM's mini computers--lack thereof
https://www.garlic.com/~lynn/2006e.html#27 X.509 and ssh
https://www.garlic.com/~lynn/2006n.html#56 AT&T Labs vs. Google Labs - R&D History
from long ago and far away ...
Date: 9/12/82
From: wheeler
Subject: VM Trip 6/19 to 7/29
This summer I visited four European locations to review VM/370 use and
teach VM/370 classes. The locations were Orleans France, Zurich
Switzerland, Stockholm Sweden, and Boeblingen Germany. In addition, on
the return trip, I stopped in London and visited a couple UK
locations, gave a talk to a group of UK SEs, and made a customer call
at Imperial College.
The locations represent a wide diversity in load, purpose,
configuration, and users. In spite of this, there was a large
commonality in the problems they face.
I spent two weeks at Orleans, France teaching a one week VM/370
internals course and reviewing their system and projects for a week.
I had already taught the VM/370 internals course in San Jose the week
prior to going to Europe. The San Jose class included 8-10 people from
IBM education who are in the process of developing an official IBM
VM/370 internal class. I also traveled to Paris and gave an one hour
VM/370 introduction to some IBM France executives.
Orleans France is the DP administrative headquarters for IBM
France. It has a large DP machine room complex running several large
systems. Except for a 168AP, all the systems are MVS (and among other
things the AAS system for IBM France is located here). The VM 168AP
system is used primarily for the delivery of a single data base
inquiry application to IBM Branch offices in France and EMEA
headquarters in Paris. The application is referred to as BOIS (branch
office information system ... unfortunately there are also a number
of different things around in the States which are also referred to as
BOIS) and is a high level inquiry application interface allowing
complex queries to be performed against the information in the AAS
data base. Every evening the complete IBM France AAS data base is
copied from the MVS system to various CMS minidisks. The BOIS
applications are built on the APL/DI product.
BOIS was initially a pilot application project done by IBM France, but
intended for eventual used throughout IBM Europe. It has been
operational for less than a year, but the 168AP is already severely
overloaded. To help ease the problem, a 158AP was in the process of
being installed while I was there.
Follow on plans for BOIS call for the migration of the application to
a group of distributed 4341s. These 4341s would also be used to
deliver other types of data processing applications to the branch
offices (electronic mail, text processing, etc.). This project is
referred to as DDP (distributed data processing) and several
machines will be initially installed in one machine room (near the
Orly airport) to implement the pilot.
The current BOIS implementation is extremely CPU intensive even though
it is a large data base application. On the current 168AP, under peak
load, response time for inquiries can run to 30 minutes or more. In
the case of the execution of a single BOIS virtual machine, over 90%
of the elapsed time is spent in CPU consumption. To significantly
improve the performance of the application will require the CPU
consumption to be drastically reduced. The CPU requirements of BOIS
will have to be reduced by at least 70-80 percent before I/O activity
begins to represent a significant resource bottleneck.
The new 158AP VM system for BOIS will share some of the same packs as
the 168AP. Since the available CPU is being increased by less than
30%, the increase in I/O loading on the shared packs will not be
significant. The proposed BOIS-DDP plan will further minimize the
possibility of I/O activity becoming a critical bottleneck. Only a
subset of the total AAS data will be present on a particular 4341
(only the data for the branch offices using that machine). There will
be fewer requests against the files on each drive, and the size of the
files will be smaller (requiring less search time/IOs to process each
request).
Eventually the BOIS application will be in use all over Europe. The
total amount of people time spent using BOIS will become quite
significant. Even relative insignificant improvements in BOIS
performance will represent large people time savings for the IBM
company. Using this as a justification, it should be feasible to
create a project to optimize the efficiency of the BOIS
application. The major portion of the BOIS application is APL/DI.
Without knowing anything about the APL/DI implementation, I can
suggest a couple possible areas that might result in major CPU
consumption reductions.
The HONE system in the States is heavily dependent on APL applications
for most of their services. They have discovered that what is taught
as good APL coding techniques (short, one to ten line programs)
represent extremely bad performing applications (the majority of the
CPU time is spent in the APL supervisor linkage routines). Factors of
five or more in performance improvement have been achieved by
performance optimization of critical APL applications (replacing 1-10
line programs with 30-50 line programs). Another possibility is to
recode high use functions in assembler or PLS and use one of the
numerous APL exit routines to call compiled, machine-language code.
The BOIS-DDP project has a requirement to develop new support (a
problem being faced by a large number of other VM-DDP projects, both
inside and outside the company),
• remote machines w/o on-site DP-professionals (only IBM SEs and salesman)
• hardware communication capabilities
• software communication facilities
• distributed data base support
• remote application
... snip ... top of post, old email index, HONE email
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: Metroliner telephone article Newsgroups: misc.transport.rail.americas,alt.folklore.computers Date: Fri, 01 Sep 2006 09:57:46 -0600hancock4 writes:
i remember in the early 70s doing a HONE-clone install in la defense
as part of EMEA hdqtrs moving from US to Paris ... and having a devil
of a time finding access to email back in the states
https://www.garlic.com/~lynn/subtopic.html#hone
one of the problems identified in the early 80s allowing email access from hotels supporting portable terminals/PCs ... was vulnerability study of hotel PBXs and as a result having to mandating special built encrypting modems.
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: "25th Anniversary of the Personal Computer" Newsgroups: alt.folklore.computers Date: Fri, 01 Sep 2006 12:23:26 -0600re:
another item from long ago and far away in the 2-tier/3-tier topic drift
https://www.garlic.com/~lynn/subnetwork.html#3tier
Date: 02/15/82 15:03:33
To: wheeler
xxxxxx, ibm france i/s, told me to contact you about the following
subject:
-we are presently studying a distributed data processing system, including
370 and 43xx systems, based on vm/cms, with the following characteristics:
-control of the whole system from a central vm system, including ipl and
message processing, using the remote operator console and programmable
operator facilities.
-control, from the central system, of the distribution and use of general
applications, including the release and implementation of new program
releases and the periodical delivery of updated data files.
-access from one remote location to applications running in the central
system or any other remote system, using a signon user interface, to be
designed.
any information about the above topics, including technical publications
and refences of similar existing systems would be of great help for us.
thank you for your help
yyyyyyyyy
IBM SAINTE-MARIE SAINT-JEAN-DE-BRAYE (FRANCE) - TELEX: FSIK
... snip ... top of post, old email index, HSDT email
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: chip performance ... from long ago and far away Newsgroups: alt.folklore.computers Date: Sat, 02 Sep 2006 08:47:56 -0600chip performance from long ago and far away
34 The Zenight Z-386/33
40 Open Look
46 RISC Workstations: An Update and Comparison
52 The Core of RISC Workstations
60 On CISC, RISC, Caches, and Clones
On page 49 is a table which I've abstracted some info from (I'm only
giving the double precision numbers):
Drystones-2 Whetstones Linpack price
dhry/sec kwhet/sec mflops $
Apollo DN10000 23607 13000 4.568 $94,900
w/1 cpu
DECstation 3100 13330 10000 1.36 $11,900
DG AViiON 32256 5703 .85
Everex 8820 37236 9045 .853 $14,995
HP 90000-835 21772 - 1.685 $59,500
MIPS RS2030 27760 10500 1.692 $14,000
SUN Sparc1 20000 4964 1.364
A box near the end of the article (pg. 50):
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: Hackers steal AT&T customer data Newsgroups: alt.security Date: Sat, 02 Sep 2006 09:08:30 -0600misc. update
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: "25th Anniversary of the Personal Computer" Newsgroups: alt.folklore.computers Date: Sat, 02 Sep 2006 15:14:25 -0600ref:
other activity from long ago and far away in the 2-tier/3-tier
evolution. SJR had a project to build experimental clustered vm/cms
system, in part in support of other research activity:
Date: 11/24/80 07:32:32
From: wheeler
do you know any good vm people who might be interested in coming to
s.j. research to work on vm related projects??? There are openings for
3 people this year & several more opening up next year. Currently
looking at installing 3 148s on the same floor with shared dasd,
hyperchannel, & tp. Looking at distributed computing, distributed data
base, reliable computing, cp file system, and networking. There are
probably several other "sins" which will be thrown in under the
umbrella once it gets going.
The 3 148s are for experimental work in computer science.
... snip ... top of post, old email index
Date: 11/24/80 08:46:33
From: wheeler
Will try and get together a project description & job description.
There will be several groups of people working on/with the machines &
system. R* is a (distributed) system R follow on (VM/CMS relational
data base).
System D is a distributed data base system currently using multiple
series 1 with shared dasd & some special hardware. They are now
interested to moving to 370 (& vm).
Several people are also interested working on "single system" image
for VM (ala HONE systems) but with shared spool additions, "paging"
out all control blocks & paging them back in on a different CPU (this
work includes interest from STL & probably working with groups outside
of SJR). Also a group looking at a CP file system (PAM with cp
dynamically allocating blocks).
... snip ... top of post, old email index, HONE email
system/r website:
http://www.mcjones.org/System_R/
lot of past posts mentioning system/r, original relational/sql
implementation, done on vm/cms platform
https://www.garlic.com/~lynn/submain.html#systemr
misc. past posts mentioning "pam" &/or memory mapped file system
https://www.garlic.com/~lynn/submain.html#mmap
misc. past posts mentioning HONE
https://www.garlic.com/~lynn/subtopic.html#hone
misc. past posts mentioning hsdt &/or hyperchannel
https://www.garlic.com/~lynn/subnetwork.html#hsdt
later we were to do ha/cmp product
https://www.garlic.com/~lynn/subtopic.html#hacmp
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: "25th Anniversary of the Personal Computer" Newsgroups: alt.folklore.computers Date: Sat, 02 Sep 2006 15:30:57 -0600ref:
another from long ago and far away in the evolution into 2-tier/3-tier
Date: 01/28/81 08:37:19
From: wheeler
re: 4341 vs. 3033 question; There is an Micro Design System (MDS)
group that provides services to GPD engineers on an MVS 3033 (it is an
almost self contained environment). They have just about converted MDS
to run under CMS. The plan is to offer MDS service on several
distributed VM/4341s connected to a MVS via the network. The central
machine would still be used to maintain the (very large) data base on
MSS. Individuals would "check-out" source from the central library
(that logically happens today so the additions have to be the network
routing), operate on it for several hours/days, and then return it to
the central site. Project was justified for several reasons.
1) multiple 4341s to provide same level of service as one 3033 is
cheaper.
2) desire to go to a distributed computing. Project demand for MDS
thru 1985 is larger than any conceivable no. of 3033s, 168s, etc. that
GPD would be able to acquire (not to mention the housing problem).
3) Total people & project costs when the current central 3033 went
down justified multiple "front-end" machines. Users that had their
programs already checked out would be able to continue working.
4. GPD has just completed a TSO interactive user study. The results
very closely follows a number of earlier reports on VM from YKT. Any
system response in excess of at least .5 seconds (YKT has been able to
measure it down to somewhere in the area of .25-.30 seconds) there is
a degradation in people response. Non-immediate system response
appears to upset people's thought processes in some way. Any slow down
in system response is matched by an equivalent slow done in human
response (total slowdown in productivity is twice the system
degradation). The same effect was measured in comparing local 327x
performance with remote 327x performance. Moving the 4341s out to the
engineers allows many remote 327x terminals to be replaced by local
327x terminals.
... snip ... top of post, old email index
part of the above was with respect to TSO not being able to practically achieve sub-second response. The 4341/3033 comparison was relatively easily being able to acquire collections of 4341 that would provide more aggregate throughput than 3033 (at lower cost).
some number of locations would scavenge departmental supply rooms and/or conference rooms for deploying 4341s.
part of this is evolution of two-tier server/mainframe operations
... between datacenter and distributed servers (4341s) ... somewhat
preceeding two-tier client/server ... which then evolves into 3-tier
https://www.garlic.com/~lynn/subnetwork.html#3tier
collected past posts mentioning working with bldg 14 (disk engineering)
and bldg 15 (disk product test)
https://www.garlic.com/~lynn/subtopic.html#disk
misc. past posts mentioning 4341/3033 comparisons:
https://www.garlic.com/~lynn/95.html#3 What is an IBM 137/148 ???
https://www.garlic.com/~lynn/99.html#7 IBM S/360
https://www.garlic.com/~lynn/2000c.html#83 Is a VAX a mainframe?
https://www.garlic.com/~lynn/2000d.html#7 4341 was "Is a VAX a mainframe?"
https://www.garlic.com/~lynn/2000d.html#12 4341 was "Is a VAX a mainframe?"
https://www.garlic.com/~lynn/2000d.html#82 "all-out" vs less aggressive designs (was: Re: 36 to 32 bit transition)
https://www.garlic.com/~lynn/2000e.html#57 Why not an IBM zSeries workstation?
https://www.garlic.com/~lynn/2001b.html#69 Z/90, S/390, 370/ESA (slightly off topic)
https://www.garlic.com/~lynn/2001j.html#3 YKYGOW...
https://www.garlic.com/~lynn/2001l.html#32 mainframe question
https://www.garlic.com/~lynn/2001m.html#15 departmental servers
https://www.garlic.com/~lynn/2001n.html#39 195 was: Computer Typesetting Was: Movies with source code
https://www.garlic.com/~lynn/2002d.html#7 IBM Mainframe at home
https://www.garlic.com/~lynn/2002f.html#8 Is AMD doing an Intel?
https://www.garlic.com/~lynn/2002i.html#22 CDC6600 - just how powerful a machine was it?
https://www.garlic.com/~lynn/2002i.html#23 CDC6600 - just how powerful a machine was it?
https://www.garlic.com/~lynn/2002n.html#58 IBM S/370-168, 195, and 3033
https://www.garlic.com/~lynn/2002n.html#59 IBM S/370-168, 195, and 3033
https://www.garlic.com/~lynn/2002n.html#63 Help me find pics of a UNIVAC please
https://www.garlic.com/~lynn/2003f.html#56 ECPS:VM DISPx instructions
https://www.garlic.com/~lynn/2003g.html#22 303x, idals, dat, disk head settle, and other rambling folklore
https://www.garlic.com/~lynn/2004g.html#20 Infiniband - practicalities for small clusters
https://www.garlic.com/~lynn/2004l.html#10 Complex Instructions
https://www.garlic.com/~lynn/2004m.html#17 mainframe and microprocessor
https://www.garlic.com/~lynn/2004n.html#14 360 longevity, was RISCs too close to hardware?
https://www.garlic.com/~lynn/2004n.html#50 Integer types for 128-bit addressing
https://www.garlic.com/~lynn/2004o.html#57 Integer types for 128-bit addressing
https://www.garlic.com/~lynn/2005.html#34 increasing addressable memory via paged memory?
https://www.garlic.com/~lynn/2005f.html#4 System/360; Hardwired vs. Microcoded
https://www.garlic.com/~lynn/2005n.html#11 Code density and performance?
https://www.garlic.com/~lynn/2005p.html#1 Intel engineer discusses their dual-core design
https://www.garlic.com/~lynn/2005p.html#19 address space
https://www.garlic.com/~lynn/2005q.html#30 HASP/ASP JES/JES2/JES3
https://www.garlic.com/~lynn/2005q.html#38 Intel strikes back with a parallel x86 design
https://www.garlic.com/~lynn/2005s.html#22 MVCIN instruction
https://www.garlic.com/~lynn/2005u.html#40 POWER6 on zSeries?
https://www.garlic.com/~lynn/2005u.html#44 POWER6 on zSeries?
https://www.garlic.com/~lynn/2005u.html#48 POWER6 on zSeries?
https://www.garlic.com/~lynn/2006b.html#28 Multiple address spaces
https://www.garlic.com/~lynn/2006b.html#34 Multiple address spaces
https://www.garlic.com/~lynn/2006b.html#39 another blast from the past
https://www.garlic.com/~lynn/2006i.html#33 virtual memory
https://www.garlic.com/~lynn/2006i.html#41 virtual memory
https://www.garlic.com/~lynn/2006l.html#2 virtual memory
https://www.garlic.com/~lynn/2006l.html#18 virtual memory
https://www.garlic.com/~lynn/2006m.html#27 Old Hashing Routine
https://www.garlic.com/~lynn/2006m.html#37 Curiosity
https://www.garlic.com/~lynn/2006p.html#0 DASD Response Time (on antique 3390?)
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: Device Authentication - The answer to attacks lauched using stolen passwords? Newsgroups: alt.computer.security,comp.security.misc,alt.security Date: Sat, 02 Sep 2006 19:04:20 -0600Sebastian Gottschalk writes:
however, nothing came of the anti-privacy activity at that time.
slightly related thread
https://www.garlic.com/~lynn/aadsm25.htm#0 Crypto to defend chip IP: snake oil or good idea?
https://www.garlic.com/~lynn/aadsm25.htm#1 Crypto to defend chip IP: snake oil or good idea?
https://www.garlic.com/~lynn/aadsm25.htm#2 Crypto to defend chip IP: snake oil or good idea?
https://www.garlic.com/~lynn/aadsm25.htm#3 Crypto to defend chip IP: snake oil or good idea?
https://www.garlic.com/~lynn/aadsm25.htm#4 Crypto to defend chip IP: snake oil or good idea?
https://www.garlic.com/~lynn/aadsm25.htm#5 Crypto to defend chip IP: snake oil or good idea?
https://www.garlic.com/~lynn/aadsm25.htm#6 Crypto to defend chip IP: snake oil or good idea?
https://www.garlic.com/~lynn/aadsm25.htm#7 Crypto to defend chip IP: snake oil or good idea?
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: old hypervisor email Newsgroups: alt.folklore.computers Date: Sun, 03 Sep 2006 08:07:49 -0600from long ago and far away.
obviously, email was before Worley left for hplabs, misc refs
https://www.garlic.com/~lynn/2006.html#39 What happens if CR's are directly changed
https://www.garlic.com/~lynn/2006e.html#1 About TLB in lower-level caches
https://www.garlic.com/~lynn/2006o.html#67 How the Pentium Fell Short of a 360/195
there was project to replace the wide variety of corporate
microprocessors with 801s, including the microcoded engines used in
the low-end and mid-range 370s. misc. collected posts mentioning 801
https://www.garlic.com/~lynn/subtopic.html#801
misc. past posts mentioning macrocode:
https://www.garlic.com/~lynn/2002p.html#44 Linux paging
https://www.garlic.com/~lynn/2002p.html#48 Linux paging
https://www.garlic.com/~lynn/2003.html#9 Mainframe System Programmer/Administrator market demand?
https://www.garlic.com/~lynn/2003.html#56 Wild hardware idea
https://www.garlic.com/~lynn/2005d.html#59 Misuse of word "microcode"
https://www.garlic.com/~lynn/2005d.html#60 Misuse of word "microcode"
https://www.garlic.com/~lynn/2005h.html#24 Description of a new old-fashioned programming language
https://www.garlic.com/~lynn/2005p.html#14 Multicores
https://www.garlic.com/~lynn/2005p.html#29 Documentation for the New Instructions for the z9 Processor
https://www.garlic.com/~lynn/2005u.html#40 POWER6 on zSeries?
https://www.garlic.com/~lynn/2005u.html#43 POWER6 on zSeries?
https://www.garlic.com/~lynn/2005u.html#48 POWER6 on zSeries?
https://www.garlic.com/~lynn/2006b.html#38 blast from the past ... macrocode
https://www.garlic.com/~lynn/2006c.html#9 Mainframe Jobs Going Away
https://www.garlic.com/~lynn/2006j.html#32 Code density and performance?
https://www.garlic.com/~lynn/2006j.html#35 Code density and performance?
https://www.garlic.com/~lynn/2006m.html#39 Using different storage key's
eventually PR/SM was produced for the 3090 and has since evolved
into the current LPARs (logical partitions). post related to SIE,
sort of leading up to pr/sm
https://www.garlic.com/~lynn/2006j.html#27 virtual memory
https://www.garlic.com/~lynn/2006n.html#44 Any resources on VLIW?
lots of past posts mentioning PR/SM and/or LPARs
https://www.garlic.com/~lynn/98.html#45 Why can't more CPUs virtualize themselves?
https://www.garlic.com/~lynn/98.html#57 Reliability and SMPs
https://www.garlic.com/~lynn/99.html#191 Merced Processor Support at it again
https://www.garlic.com/~lynn/2000.html#8 Computer of the century
https://www.garlic.com/~lynn/2000.html#63 Mainframe operating systems
https://www.garlic.com/~lynn/2000.html#86 Ux's good points.
https://www.garlic.com/~lynn/2000b.html#50 VM (not VMS or Virtual Machine, the IBM sort)
https://www.garlic.com/~lynn/2000b.html#51 VM (not VMS or Virtual Machine, the IBM sort)
https://www.garlic.com/~lynn/2000b.html#52 VM (not VMS or Virtual Machine, the IBM sort)
https://www.garlic.com/~lynn/2000b.html#61 VM (not VMS or Virtual Machine, the IBM sort)
https://www.garlic.com/~lynn/2000b.html#62 VM (not VMS or Virtual Machine, the IBM sort)
https://www.garlic.com/~lynn/2000c.html#8 IBM Linux
https://www.garlic.com/~lynn/2000c.html#50 Does the word "mainframe" still have a meaning?
https://www.garlic.com/~lynn/2000c.html#68 Does the word "mainframe" still have a meaning?
https://www.garlic.com/~lynn/2000c.html#76 Is a VAX a mainframe?
https://www.garlic.com/~lynn/2000e.html#20 Is Al Gore The Father of the Internet?^
https://www.garlic.com/~lynn/2000f.html#78 TSS ancient history, was X86 ultimate CISC? designs)
https://www.garlic.com/~lynn/2000g.html#3 virtualizable 360, was TSS ancient history
https://www.garlic.com/~lynn/2001.html#34 Competitors to SABRE?
https://www.garlic.com/~lynn/2001b.html#72 Z/90, S/390, 370/ESA (slightly off topic)
https://www.garlic.com/~lynn/2001d.html#67 Pentium 4 Prefetch engine?
https://www.garlic.com/~lynn/2001e.html#5 SIMTICS
https://www.garlic.com/~lynn/2001e.html#61 Estimate JCL overhead
https://www.garlic.com/~lynn/2001f.html#17 Accounting systems ... still in use? (Do we still share?)
https://www.garlic.com/~lynn/2001f.html#23 MERT Operating System & Microkernels
https://www.garlic.com/~lynn/2001h.html#2 Alpha: an invitation to communicate
https://www.garlic.com/~lynn/2001h.html#33 D
https://www.garlic.com/~lynn/2001l.html#24 mainframe question
https://www.garlic.com/~lynn/2001m.html#38 CMS under MVS
https://www.garlic.com/~lynn/2001n.html#17 CM-5 Thinking Machines, Supercomputers
https://www.garlic.com/~lynn/2001n.html#26 Open Architectures ?
https://www.garlic.com/~lynn/2001n.html#31 Hercules etc. IBM not just missing a great opportunity...
https://www.garlic.com/~lynn/2001n.html#32 Hercules etc. IBM not just missing a great opportunity...
https://www.garlic.com/~lynn/2002b.html#44 PDP-10 Archive migration plan
https://www.garlic.com/~lynn/2002c.html#53 VAX, M68K complex instructions (was Re: Did Intel Bite Off More Than It Can Chew?)
https://www.garlic.com/~lynn/2002d.html#31 2 questions: diag 68 and calling convention
https://www.garlic.com/~lynn/2002e.html#25 Crazy idea: has it been done?
https://www.garlic.com/~lynn/2002e.html#75 Computers in Science Fiction
https://www.garlic.com/~lynn/2002f.html#6 Blade architectures
https://www.garlic.com/~lynn/2002f.html#57 IBM competes with Sun w/new Chips
https://www.garlic.com/~lynn/2002n.html#6 Tweaking old computers?
https://www.garlic.com/~lynn/2002n.html#27 why does wait state exist?
https://www.garlic.com/~lynn/2002n.html#28 why does wait state exist?
https://www.garlic.com/~lynn/2002o.html#0 Home mainframes
https://www.garlic.com/~lynn/2002o.html#15 Home mainframes
https://www.garlic.com/~lynn/2002o.html#16 Home mainframes
https://www.garlic.com/~lynn/2002o.html#18 Everything you wanted to know about z900 from IBM
https://www.garlic.com/~lynn/2002p.html#4 Running z/VM 4.3 in LPAR & guest v-r or v=f
https://www.garlic.com/~lynn/2002p.html#40 Linux paging
https://www.garlic.com/~lynn/2002p.html#44 Linux paging
https://www.garlic.com/~lynn/2002p.html#45 Linux paging
https://www.garlic.com/~lynn/2002p.html#46 Linux paging
https://www.garlic.com/~lynn/2002p.html#48 Linux paging
https://www.garlic.com/~lynn/2002p.html#54 Newbie: Two quesions about mainframes
https://www.garlic.com/~lynn/2002p.html#55 Running z/VM 4.3 in LPAR & guest v-r or v=f
https://www.garlic.com/~lynn/2002q.html#26 LISTSERV Discussion List For USS Questions?
https://www.garlic.com/~lynn/2003.html#9 Mainframe System Programmer/Administrator market demand?
https://www.garlic.com/~lynn/2003.html#14 vax6k.openecs.org rebirth
https://www.garlic.com/~lynn/2003.html#15 vax6k.openecs.org rebirth
https://www.garlic.com/~lynn/2003.html#56 Wild hardware idea
https://www.garlic.com/~lynn/2003c.html#41 How much overhead is "running another MVS LPAR" ?
https://www.garlic.com/~lynn/2003f.html#56 ECPS:VM DISPx instructions
https://www.garlic.com/~lynn/2003k.html#9 What is timesharing, anyway?
https://www.garlic.com/~lynn/2003l.html#12 Why are there few viruses for UNIX/Linux systems?
https://www.garlic.com/~lynn/2003l.html#41 Secure OS Thoughts
https://www.garlic.com/~lynn/2003m.html#32 SR 15,15 was: IEFBR14 Problems
https://www.garlic.com/~lynn/2003m.html#37 S/360 undocumented instructions?
https://www.garlic.com/~lynn/2003n.html#13 CPUs with microcode ?
https://www.garlic.com/~lynn/2003n.html#29 Architect Mainframe system - books/guidenance
https://www.garlic.com/~lynn/2003o.html#52 Virtual Machine Concept
https://www.garlic.com/~lynn/2004b.html#58 Oldest running code
https://www.garlic.com/~lynn/2004c.html#4 OS Partitioning and security
https://www.garlic.com/~lynn/2004c.html#5 PSW Sampling
https://www.garlic.com/~lynn/2004d.html#6 Memory Affinity
https://www.garlic.com/~lynn/2004e.html#26 The attack of the killer mainframes
https://www.garlic.com/~lynn/2004e.html#28 The attack of the killer mainframes
https://www.garlic.com/~lynn/2004f.html#47 Infiniband - practicalities for small clusters
https://www.garlic.com/~lynn/2004g.html#15 Infiniband - practicalities for small clusters
https://www.garlic.com/~lynn/2004k.html#37 Wars against bad things
https://www.garlic.com/~lynn/2004k.html#43 Vintage computers are better than modern crap !
https://www.garlic.com/~lynn/2004m.html#41 EAL5
https://www.garlic.com/~lynn/2004m.html#49 EAL5
https://www.garlic.com/~lynn/2004n.html#10 RISCs too close to hardware?
https://www.garlic.com/~lynn/2004o.html#13 Integer types for 128-bit addressing
https://www.garlic.com/~lynn/2004o.html#32 What system Release do you use... OS390? z/os? I'm a Vendor S
https://www.garlic.com/~lynn/2004p.html#37 IBM 3614 and 3624 ATM's
https://www.garlic.com/~lynn/2004q.html#18 PR/SM Dynamic Time Slice calculation
https://www.garlic.com/~lynn/2004q.html#72 IUCV in VM/CMS
https://www.garlic.com/~lynn/2004q.html#76 Athlon cache question
https://www.garlic.com/~lynn/2005.html#6 [Lit.] Buffer overruns
https://www.garlic.com/~lynn/2005b.html#5 Relocating application architecture and compiler support
https://www.garlic.com/~lynn/2005c.html#56 intel's Vanderpool and virtualization in general
https://www.garlic.com/~lynn/2005d.html#59 Misuse of word "microcode"
https://www.garlic.com/~lynn/2005d.html#70 Virtual Machine Hardware
https://www.garlic.com/~lynn/2005d.html#74 [Lit.] Buffer overruns
https://www.garlic.com/~lynn/2005f.html#45 Moving assembler programs above the line
https://www.garlic.com/~lynn/2005f.html#59 Where should the type information be: in tags and descriptors
https://www.garlic.com/~lynn/2005h.html#13 Today's mainframe--anything to new?
https://www.garlic.com/~lynn/2005h.html#19 Blowing My Own Horn
https://www.garlic.com/~lynn/2005h.html#24 Description of a new old-fashioned programming language
https://www.garlic.com/~lynn/2005j.html#16 Performance and Capacity Planning
https://www.garlic.com/~lynn/2005j.html#19 Performance and Capacity Planning
https://www.garlic.com/~lynn/2005k.html#35 Determining processor status without IPIs
https://www.garlic.com/~lynn/2005k.html#43 Determining processor status without IPIs
https://www.garlic.com/~lynn/2005k.html#49 Determining processor status without IPIs
https://www.garlic.com/~lynn/2005l.html#25 PKI Crypto and VSAM RLS
https://www.garlic.com/~lynn/2005l.html#26 ESCON to FICON conversion
https://www.garlic.com/~lynn/2005m.html#16 CPU time and system load
https://www.garlic.com/~lynn/2005n.html#12 Code density and performance?
https://www.garlic.com/~lynn/2005p.html#14 Multicores
https://www.garlic.com/~lynn/2005p.html#29 Documentation for the New Instructions for the z9 Processor
https://www.garlic.com/~lynn/2005p.html#38 storage key question
https://www.garlic.com/~lynn/2005r.html#42 winscape?
https://www.garlic.com/~lynn/2005s.html#23 winscape?
https://www.garlic.com/~lynn/2005s.html#36 Filemode 7-9?
https://www.garlic.com/~lynn/2005u.html#40 POWER6 on zSeries?
https://www.garlic.com/~lynn/2005u.html#43 POWER6 on zSeries?
https://www.garlic.com/~lynn/2005u.html#48 POWER6 on zSeries?
https://www.garlic.com/~lynn/2006.html#17 {SPAM?} DCSS as SWAP disk for z/Linux
https://www.garlic.com/~lynn/2006.html#31 Is VIO mandatory?
https://www.garlic.com/~lynn/2006b.html#38 blast from the past ... macrocode
https://www.garlic.com/~lynn/2006c.html#1 Multiple address spaces
https://www.garlic.com/~lynn/2006c.html#9 Mainframe Jobs Going Away
https://www.garlic.com/~lynn/2006e.html#15 About TLB in lower-level caches
https://www.garlic.com/~lynn/2006h.html#30 The Pankian Metaphor
https://www.garlic.com/~lynn/2006j.html#27 virtual memory
https://www.garlic.com/~lynn/2006j.html#29 How to implement Lpars within Linux
https://www.garlic.com/~lynn/2006j.html#33 How to implement Lpars within Linux
https://www.garlic.com/~lynn/2006j.html#35 Code density and performance?
https://www.garlic.com/~lynn/2006l.html#19 virtual memory
https://www.garlic.com/~lynn/2006l.html#22 Virtual Virtualizers
https://www.garlic.com/~lynn/2006l.html#23 Virtual Virtualizers
https://www.garlic.com/~lynn/2006l.html#25 Mainframe Linux Mythbusting (Was: Using Java in batch on z/OS?)
https://www.garlic.com/~lynn/2006l.html#43 One or two CPUs - the pros & cons
https://www.garlic.com/~lynn/2006m.html#19 Mainframe Linux Mythbusting
https://www.garlic.com/~lynn/2006m.html#39 Using different storage key's
https://www.garlic.com/~lynn/2006n.html#10 Not Your Dad's Mainframe: Little Iron
https://www.garlic.com/~lynn/2006n.html#42 Why is zSeries so CPU poor?
https://www.garlic.com/~lynn/2006o.html#27 oops
https://www.garlic.com/~lynn/2006o.html#38 hardware virtualization slower than software?
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Slow-Going For Next-Generation Threat-Scoring System Newsgroups: alt.computer.security Date: Sun, 03 Sep 2006 09:14:37 -0600Slow-Going For Next-Generation Threat-Scoring System - CVSS, NIAC, Cisco, symantec, Microsoft, ISS, eBay
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: Materiel and graft Newsgroups: alt.folklore.computers Date: Sun, 03 Sep 2006 12:51:41 -0600Brian Inglis writes:
1971 Xerox PARC EARS (Ethernet, Alto, Research character generator, Scanned laser output terminal) laser printer 1976 IBM 3800 mainframe datacentre (@ Woolworth) 1977 Xerox 9700 mainframe datacentre 1979 IBM 6670 departmental office (copier sized) 1982 Canon LBP-10 (desktop) 1984 HP LaserJet 1985 Apple LaserWriterin fact, 6670 could be considered a (ibm) copier3 with computer interface. it did inherit "duplex" (being able to print on both sides) from copier3. 6670 formater started out being a flavor of (cms) script ... originally done at the science center
recent ref:
https://www.garlic.com/~lynn/2006p.html#27 What part of z/OS is the OS?
and where gml was invented (precursor to sgml, html, xml, etc)
https://www.garlic.com/~lynn/submain.html#sgml
some number of people at sjr worked on sherpa enhancement to 6670 and then later, adding postscript support to sherpa (at least one of the people on the project, left and went to adobe).
note on adobe postscript
http://www.adobe.com/products/postscript/pdfs/postscript_is_20.pdf
from long ago and far away ...
Date: 03/04/82 10:26-PM
From: somebody in san jose
To: somebody at boulder
CC: wheeler
Lynn Wheeler forwarded me your mail about the Boulder satelite link.
We have a joint project between two departments here in San Jose
Research which is building a 6670 laser printer/copier/scanner. I
should rather say that we are adding a scanner to the Boulder built
6670 laser printer/copier. My involvement is that we have built an
APA (all points addressable) control unit for the 6670 for printing
arbitrarily complex pages. We call it SHERPA. In fact, we installed
a copy of our controller in Boulder in December.
It has a 1M byte storage that hold a complete page image for printing.
It is serialized and sent to the 6670 at a 10Mhz data rate (the 6670
laser speed). When we were designing the printer we also made
allowances for the hardware to run "backward", taking a 10Mhz signal
and filling the page image storage. Another group headed by zzzzz San
Jose Research, has modified a 6670 to allow the laser to scan the
toned photoconductor drum. We can dump the image into our full page
bit image storage.
One experiment that could be done with this high-speed scanner is to
use it as a "remote copier". One could put one on each end of a
high-speed data link and scan on one machine, transmit to the other
and print on it. It is conceivable that this could be done at 35
pages/minute.
We currently have a 56KB link between our SHERPA control unit and our
3033 host. On that bisync link it takes us 2 minutes to transmit a
full page (uncompressed) bit image of a page. While that is not the
mode for which we designed SHERPA it none-the-less supports it. We
designed it to behave more like a photocomposer, taking coded
character information with font selections and variable (flexible)
spacing. The SHERPA also supports including images with the printed
text and, in fact, the images can be as large as the whole page,
providing the facimile like capability.
What I would envision is encoding the scanned image inside the SHERPA,
itself, to reduce the data from roughly 670,000 bytes/page to maybe
100,000 bytes. These would be sent to the 3033 host to be transmitted
to the remote site. There the process would be reversed to form the
printed image. Since we already have a SHERPA in Boulder and in fact
are modifying a second 6670 for the manager of Boulder printer
products, zzzzzzz, for Boulder experimentation, it would be the ideal
set up for a high-speed link to demonstrate such a system. I would
envision a link from host VM to VM. If it were 56KB and we could get
a compression ratio of 4 to 1 or better with a simple algorithm, we
could send about 2 pages/minute. One could possibly do much better.
I am typing this at home just before bedtime so am not too sure if it
is very easy to read, but will send it on anyway. If you would like
to discuss this further please call me. You may also wish to look at
the SHERPA there: contact zzzzzz or zzzzz. They have the SHERPA set
up in Bldg. 22 (print only).
I would imagine that zzzzz would give this kind of project some
support. This is one way to make the 6670 do what the TV commercials
show it doing.
... snip ... top of post, old email index
misc. past posts mentioning 3800 and/or 6670
https://www.garlic.com/~lynn/99.html#42 Enter fonts (was Re: Unix case-sensitivity: how did it originate?
https://www.garlic.com/~lynn/99.html#43 Enter fonts (was Re: Unix case-sensitivity: how did it originate?
https://www.garlic.com/~lynn/99.html#52 Enter fonts (was Re: Unix case-sensitivity: how did it originate?
https://www.garlic.com/~lynn/2000b.html#29 20th March 2000
https://www.garlic.com/~lynn/2000d.html#81 Coloured IBM DASD
https://www.garlic.com/~lynn/2000e.html#1 What good and old text formatter are there ?
https://www.garlic.com/~lynn/2001b.html#50 IBM 705 computer manual
https://www.garlic.com/~lynn/2001g.html#5 New IBM history book out
https://www.garlic.com/~lynn/2001n.html#31 Hercules etc. IBM not just missing a great opportunity...
https://www.garlic.com/~lynn/2002d.html#8 Security Proportional to Risk (was: IBM Mainframe at home)
https://www.garlic.com/~lynn/2002g.html#52 Spotting BAH Claims to Fame
https://www.garlic.com/~lynn/2002h.html#7 disk write caching (was: ibm icecube -- return of
https://www.garlic.com/~lynn/2002i.html#12 CDC6600 - just how powerful a machine was it?
https://www.garlic.com/~lynn/2002k.html#42 MVS 3.8J and NJE via CTC
https://www.garlic.com/~lynn/2002m.html#50 Microsoft's innovations [was:the rtf format]
https://www.garlic.com/~lynn/2002m.html#52 Microsoft's innovations [was:the rtf format]
https://www.garlic.com/~lynn/2002o.html#24 IBM Selectric as printer
https://www.garlic.com/~lynn/2002o.html#29 6670
https://www.garlic.com/~lynn/2003c.html#43 Early attempts at console humor?
https://www.garlic.com/~lynn/2003k.html#45 text character based diagrams in technical documentation
https://www.garlic.com/~lynn/2003k.html#52 dissassembled code
https://www.garlic.com/~lynn/2004c.html#1 Oldest running code
https://www.garlic.com/~lynn/2004d.html#13 JSX 328x printing (portrait)
https://www.garlic.com/~lynn/2004g.html#17 Infiniband - practicalities for small clusters
https://www.garlic.com/~lynn/2004g.html#18 Infiniband - practicalities for small clusters
https://www.garlic.com/~lynn/2004k.html#48 Xah Lee's Unixism
https://www.garlic.com/~lynn/2004l.html#61 Shipwrecks
https://www.garlic.com/~lynn/2005b.html#25 360POO
https://www.garlic.com/~lynn/2005f.html#34 [Lit.] Buffer overruns
https://www.garlic.com/~lynn/2005f.html#48 1403 printers
https://www.garlic.com/~lynn/2005f.html#51 1403 printers
https://www.garlic.com/~lynn/2005f.html#52 1403 printers
https://www.garlic.com/~lynn/2005f.html#54 1403 printers
https://www.garlic.com/~lynn/2005k.html#58 Book on computer architecture for beginners
https://www.garlic.com/~lynn/2005l.html#0 Book on computer architecture for beginners
https://www.garlic.com/~lynn/2005r.html#29 Job seperators
https://www.garlic.com/~lynn/2006b.html#20 Seeking Info on XDS Sigma 7 APL
https://www.garlic.com/~lynn/2006k.html#48 Hey! Keep Your Hands Out Of My Abstraction Layer!
https://www.garlic.com/~lynn/2006n.html#0 The System/360 Model 20 Wasn't As Bad As All That
https://www.garlic.com/~lynn/2006n.html#4 The System/360 Model 20 Wasn't As Bad As All That
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: what's the difference between LF(Line Fee) and NL (New line) ? Newsgroups: bit.listserv.ibm-main Date: Mon, 04 Sep 2006 07:57:41 -0600ltsai85613@ibm-main.lst (Tsai Laurence) writes:
summary rfc 318 telnet protocol
https://www.garlic.com/~lynn/rfcidx1.htm#318
318
[Ad hoc Telnet Protocol], Postel J., 1972/04/03 (23pp)
(.txt=34928) (Updated by 435) (Updates 158) (Ref'ed By 739, 750,
755, 758, 762, 770)
clicking on the ".txt=" field in rfc summary retrieves the actual rfc
from rfc 318 ...
Telnet defines the end of a line to be indicated by the ASCII
character pair CR LR. Several of the real devices in the world have
only a single new line (NL) function. Several of the computer
systems have in some programs used the CR and LF functions to have
semantic meaning larger than the format effect they provide.
Further, several computer systems allow the CR and LF functions to be
used separately (e.g., such that a line may be overprinted). One
problem, for those Telnet (user) programs required to map the NVT
into a device which only has a NL function, is how is the CR LF to be
dealt with. One solution is to examine the character following the
CR. If an LF is found, then perform the NL function; if anything
else is found then back space to the beginning of the line. Another
problem is the case of a computer system which locally uses period,
".", to cause the new line function and which uses, in some programs,
CR and LF for semantically significant operations. Suppose the user
Telnet sends the sequence CR LF. Does this mean "new line" or the
"CR operation" followed by the "LF operation "? A solution to this
problem it to require that Telnet programs send a CR NOT intended to
be part of a CR LF pair as a CR NUL pair. Then the receiving program
can always hold a CR and examine the next character to determine if a
new line function is intended. This solution is strongly
recommended.
... and ..
Line Feed (LF) 10 Moves the printer to next line (keeping
the same horizontal position).
Carriage Return (CR) 13 Moves the printer to the left margin
of the current line.
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: "25th Anniversary of the Personal Computer" Newsgroups: alt.folklore.computers Date: Mon, 04 Sep 2006 09:11:03 -0600krw writes:
both FCS (fiber channel standard) and SCI (scallable coherent interface) provided for asynchronous operation.
circa 1990, 9333s had 80mbit/sec serial copper ... basically doing asynchronous SCSI commands over the serial interfaces ... to potentially a drawer of drives. a single drive was somewhat better than a signle drive scsi ... but four drive configuration had significantly higher aggregate thruput than four drive scsi configuration (in large part because of the asynchronous processing). this eventually evolved into 160mbit SSA (Serial Storage Architecture), i.e. it was so much raw data transfer ... but also minimized latencies by allowing asynchronous operation.
minor reference from long ago and far away
https://www.garlic.com/~lynn/95.html#13 SSA
old news article from 1998
SSA technology breaks 3000 IO bottlenecks
http://www.3000newswire.com/subscribers/SSAPrimer.html
from above:
Serial SCSI is the industry's answer to IO problems. In the
early 90s, IBM recognized that they not only had to make disks faster,
they had to make the interface smarter. They invented and patented two
new SCSI interfaces: FibreChannel and SSA. Both use the SCSI command
set and are open ANSI standards. Since no vendor yet offers a
fibre-channel solution for HP 3000s, this article will discuss the
merits of incorporating SSA technology.
... snip ...
part of above may be slightly misstated. 80mbit serial copper was done by Hursley lab (which evolved into SSA).
FCS was different. It was being backed by LLNL ... they had a non-blocking serial copper switch in the mid-80s that they were trying to standardized with 1gbit fiber (fiber channel standard). FCS can also be used for processor-to-processor communication (i.e. tcp/ip can ride on FCS in addition to SCSI commands riding on FCS).
One of the Austin engineers had taken some fiber technology that had been knocking around POK since the 70s ... and enhanced it to run about ten percent faster and use much less expensive optical drivers. The old-time version eventually came out of POK as mainframe "ESCON". The enhanced version came out for the RS/6000 as SLA (serial link adapter). The engineer wanted to then followup with a (proprietary) 800mbit version of SLA. We spent six months convincing him to drop the proprietary effort and instead get involved with the FCS standardization effort (where he became the document editor for the standard).
misc. past posts mentioning FCS, SCI, SSA, SLA, etc.
https://www.garlic.com/~lynn/96.html#15 tcp/ip
https://www.garlic.com/~lynn/98.html#30 Drive letters
https://www.garlic.com/~lynn/2000c.html#56 Does the word "mainframe" still have a meaning?
https://www.garlic.com/~lynn/2000c.html#59 Does the word "mainframe" still have a meaning?
https://www.garlic.com/~lynn/2000c.html#68 Does the word "mainframe" still have a meaning?
https://www.garlic.com/~lynn/2000d.html#14 FW: RS6000 vs IBM Mainframe
https://www.garlic.com/~lynn/2000f.html#31 OT?
https://www.garlic.com/~lynn/2001.html#12 Small IBM shops
https://www.garlic.com/~lynn/2001.html#18 Disk caching and file systems. Disk history...people forget
https://www.garlic.com/~lynn/2001.html#46 Small IBM shops
https://www.garlic.com/~lynn/2001d.html#69 Block oriented I/O over IP
https://www.garlic.com/~lynn/2001e.html#22 High Level Language Systems was Re: computer books/authors (Re: FA:
https://www.garlic.com/~lynn/2001f.html#11 Climate, US, Japan & supers query
https://www.garlic.com/~lynn/2001j.html#23 OT - Internet Explorer V6.0
https://www.garlic.com/~lynn/2001k.html#22 ESCON Channel Limits
https://www.garlic.com/~lynn/2001m.html#25 ESCON Data Transfer Rate
https://www.garlic.com/~lynn/2002e.html#7 Bus & Tag, possible length/distance?
https://www.garlic.com/~lynn/2002e.html#32 What goes into a 3090?
https://www.garlic.com/~lynn/2002f.html#6 Blade architectures
https://www.garlic.com/~lynn/2002f.html#7 Blade architectures
https://www.garlic.com/~lynn/2002f.html#11 Blade architectures
https://www.garlic.com/~lynn/2002g.html#33 ESCON Distance Limitations - Why ?
https://www.garlic.com/~lynn/2002h.html#78 Q: Is there any interest for vintage Byte Magazines from 1983
https://www.garlic.com/~lynn/2002j.html#15 Unisys A11 worth keeping?
https://www.garlic.com/~lynn/2002p.html#34 VSE (Was: Re: Refusal to change was Re: LE and COBOL)
https://www.garlic.com/~lynn/2003d.html#57 Another light on the map going out
https://www.garlic.com/~lynn/2003h.html#0 Escon vs Ficon Cost
https://www.garlic.com/~lynn/2003o.html#54 An entirely new proprietary hardware strategy
https://www.garlic.com/~lynn/2003o.html#64 1teraflops cell processor possible?
https://www.garlic.com/~lynn/2003p.html#43 Mainframe Emulation Solutions
https://www.garlic.com/~lynn/2004d.html#68 bits, bytes, half-duplex, dual-simplex, etc
https://www.garlic.com/~lynn/2004l.html#15 Xah Lee's Unixism
https://www.garlic.com/~lynn/2004n.html#45 Shipwrecks
https://www.garlic.com/~lynn/2004p.html#29 FW: Is FICON good enough, or is it the only choice we get?
https://www.garlic.com/~lynn/2005.html#50 something like a CTC on a PC
https://www.garlic.com/~lynn/2005e.html#12 Device and channel
https://www.garlic.com/~lynn/2005e.html#13 Device and channel
https://www.garlic.com/~lynn/2005h.html#7 IBM 360 channel assignments
https://www.garlic.com/~lynn/2005h.html#13 Today's mainframe--anything to new?
https://www.garlic.com/~lynn/2005j.html#13 Performance and Capacity Planning
https://www.garlic.com/~lynn/2005l.html#26 ESCON to FICON conversion
https://www.garlic.com/~lynn/2005m.html#35 IBM's mini computers--lack thereof
https://www.garlic.com/~lynn/2005m.html#46 IBM's mini computers--lack thereof
https://www.garlic.com/~lynn/2005m.html#55 54 Processors?
https://www.garlic.com/~lynn/2005r.html#14 Intel strikes back with a parallel x86 design
https://www.garlic.com/~lynn/2005u.html#23 Channel Distances
https://www.garlic.com/~lynn/2005v.html#0 DMV systems?
https://www.garlic.com/~lynn/2006c.html#40 IBM 610 workstation computer
https://www.garlic.com/~lynn/2006i.html#34 TOD clock discussion
https://www.garlic.com/~lynn/2006l.html#43 One or two CPUs - the pros & cons
https://www.garlic.com/~lynn/2006m.html#52 TCP/IP and connecting z to alternate platforms
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: "25th Anniversary of the Personal Computer" Newsgroups: alt.folklore.computers Date: Mon, 04 Sep 2006 10:19:17 -0600re:
from long ago and far away ... Harrier is code name for what became
9333 (which later turned into SSA). Note that the last item mentions
"checksum disks" ... this is commoningly referred to now as raid.
Date: 10/11/88 16:54:55
To: wheeler
----------------------------------------------------------------------
Hursley trip issues/facts/enhancements:
- DASD Format: (fact)
- Track format, ECC, ERPs functionally identical to SCSI Redwing.
Comment: Potentially,by changing SCSI Redwing controller card to
serial card, the drive can be attached under Harrier.
- Serial link: (fact)
- Full duplex link
- Packet Multiplexed
- 9 MB/S speed
- Packet format like X.25
... snip ... and the last item:
- Checksum disks
- This is for availability.
- Will have WRITE performance impact
Comment: This feature is used by A/S 400 or S/38. It has
questionable value in Rios. If no comment, this feature will
be rejected.
... snip ... top of post, old email index
old post on raid
https://www.garlic.com/~lynn/2002e.html#4 Mainframers: Take back the light (spotlight, that is)
https://www.garlic.com/~lynn/2004d.html#29 cheaper low quality drives
the above includes following ref from a URL
1978
First patent for RAID (Redundant Arrays of Independent Disks)
technology. IBM subsequently co-sponsored the research by the
University of California at Berkeley that led to the initial
definition of RAID levels in 1987.
The first two-speed tape unit, raising streaming speeds to 160
kb/second.
Hierarchical Storage Manager (HSM), which provided customers
system-delivered migration of inactive data from disk to less
expensive tape.
... snip ...
however, that URL no longer exists ...
so to wiki
https://en.wikipedia.org/wiki/Redundant_array_of_independent_disks
... from above:
Norman Ken Ouchi at IBM was awarded U.S. Patent 4,092,732 titled
"System for recovering data stored in failed memory unit" in 1978 and
the claims for this patent describe what would later be termed RAID 5
with full stripe writes. This 1978 patent also mentions that disk
mirroring or duplexing (what would later be termed RAID 1) and
protection with dedicated parity (that would later be termed RAID 4)
were prior art at that time.
RAID technology was first defined by a group of computer scientists at
the University of California, Berkeley in 1987. The scientists studied
the possibility of using two or more disks to appear as a single
device to the host system.
In 1988, RAID levels 1 through 5 were formally defined by David
A. Patterson, Garth A. Gibson and Randy H. Katz in the paper, "A Case
for Redundant Arrays of Inexpensive Disks (RAID)". This was published
in the SIGMOD Conference 1988: pp 109-116. The term "RAID" was first
introduced in this paper; it spawned the entire disk array industry.
... snip ...
and for a little more topic drft, other reference to SSA
https://www.garlic.com/~lynn/95.html#13
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: Device Authentication - The answer to attacks lauched using stolen passwords? Newsgroups: alt.computer.security,comp.security.misc,alt.security Date: Mon, 04 Sep 2006 12:20:21 -0600re:
for slight other drift, i gave a talk on assurance and aads chip strawman
https://www.garlic.com/~lynn/x959.html#aads
in the TPM track at the spring 2001 intel developer's forum
https://www.garlic.com/~lynn/index.html#presentation
some comments on the talk from that time
https://www.garlic.com/~lynn/aadsm5.htm#asrn1
https://www.garlic.com/~lynn/aadsm5.htm#asrn2
https://www.garlic.com/~lynn/aadsm5.htm#asrn3
https://www.garlic.com/~lynn/aadsm5.htm#asrn4
the person heading up the tpm effort was in the front row ... and i quipped that after the past couple years the tpm chip design was starting to now look more and more like aads chip strawman ... and he quipped back that it was because I didn't have a committee of 200 people helping design/specify the chip.
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: Materiel and graft Newsgroups: alt.folklore.computers Date: Mon, 04 Sep 2006 12:58:07 -0600re:
and for some additional drift ... from the TeX Users Group web site
http://www.tug.org/
an old "TUGboat" v6n2 (from 1985)
https://www.tug.org/TUGboat/Articles/tb06-2/tb12site.pdf
has a slac site report on use with vm/cms ... which mentions Sherpa (apa6670):
from above ...
The VM/CMS port of is a combination of efforts of many people. WEB
change files for preliminary versions of TeX were brought to the TUG
meeting in August 1983 and given to David Fuchs who combined them into
a definitive version on the VM system at Stanford Linear Accelerator
Center. The original change files were supplied by Roger Chaffee of
SLAC (now at Metaphor), Craig Platt of the University of Manitoba, and
Peter Sih of IBM Palo Alto Scientific Center. Bernd Schulze of the
University of Bonn also contributed his experience from bringing up a
preliminary TeX under CMS.
... snip ... and
The tape includes four utilities to interface TeX to the IBM 4250
electro-erosion printer and 3800 model 3 page printer, all of which
were written by Pete Sih. The first utility, DVI4250, converts a DVI
file into a format edible by the 4250. You still need the CDPF device
driver that comes with the 4250. The second utility, DVI38PP does the
same for the 3800 model 3. If you have a Sherpa (or APA6670), its
current-release software has an interface to accept the 3800 data
stream. The third utility, PXLCVT, converts the old METAFONT's PXL
fonts into 4250 format and 3800 format. The fourth utility, FONTPL,
makes W-type property-list (PL) files from IBM font files of filetype
FONT4250 and FONT38PP.
... snip ...
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: what's the difference between LF(Line Fee) and NL (New line) ? Newsgroups: bit.listserv.ibm-main,alt.folklore.computers Date: Mon, 04 Sep 2006 19:13:38 -0600jsavard writes:
last week of jan68, three people from the science center
https://www.garlic.com/~lynn/subtopic.html#545tech
came out from the science center to install cp67.
at the time, cp67 had support for (doing automatic terminal recognition) for 2741 and 1050s. the university had some ascii tty33s ... so i found myself adding ascii tty terminal support to cp67. this included having to decide how some ascii characters mapped to ebcdic and back again.
i thot i could do the implementation so that tty support would be merged into the existing cp67 automatic terminal recognition ... which sort of worked. I thot the 2702 sad command which switched line scanner between supported terminal types. this worked fine for leased lines and terminals with the same baud rate. however, 2702 had shortcut ... while sad command could change the line scanner on each port/line ... the oscillator fixing the baud rate was hard wired to each port.
this short comming led to a univ. project to build our own terminal
control unit, reverse engineer the channel interface and build our own
channel interface card for an interdata/3 programmed to emulate 2702
... with the added capability that it would automate baud rate
determination. somebody then did a write-up blaming four of
us for the plug control unit business:
https://www.garlic.com/~lynn/submain.html#360pcm
here is a story about the tty support later resulting in 27
cp67 crashes on a single day.
https://www.multicians.org/thvv/360-67.html
I had done some one byte truncations related to tty line length ... and a local modification was made to handle some sort of ascii device (plotter?) with line length on the order of 1k(?) ... the maximum line length was increased w/o changing the one byte fiddling.
later, the claim was that a primary motivation for FS
https://www.garlic.com/~lynn/submain.html#futuresys
effort was as counter to plug compatible controller business ...
from the following
https://www.ecole.org/en/session/49-the-rise-and-fall-of-ibm
https://www.ecole.org/en/session/49-the-rise-and-fall-of-ibm
IBM tried to react by launching a major project called the 'Future
System' (FS) in the early 1970's. The idea was to get so far ahead
that the competition would never be able to keep up, and to have such
a high level of integration that it would be impossible for
competitors to follow a compatible niche strategy. However, the
project failed because the objectives were too ambitious for the
available technology. Many of the ideas that were developed were
nevertheless adapted for later generations. Once IBM had acknowledged
this failure, it launched its 'box strategy', which called for
competitiveness with all the different types of compatible
sub-systems. But this proved to be difficult because of IBM's cost
structure and its R&D spending, and the strategy only resulted in a
partial narrowing of the price gap between IBM and its rivals.
... &
This first quiet warning was taken seriously: 2,500 people were
mobilised for the FS project. Those in charge had the right to choose
people from any IBM units. I was working in Paris when I was picked
out of the blue to be sent to New York. Proof of the faith people had
in IBM is that I never heard of anyone refusing to move, nor
regretting it. However, other quiet warnings were taken less
seriously.
... snip ...
as i've mentioned a number of times in the past, i wasn't very respective about the FS effort ... drawing an analogy with some cult film that been playing down in central sq for over a decade ... something about the inmates being in charge of the institution.
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: what's the difference between LF(Line Fee) and NL (New line) ? Newsgroups: bit.listserv.ibm-main,alt.folklore.computers Date: Tue, 05 Sep 2006 07:09:12 -0600Peter Flass writes:
that not only applies to terminal stuff ... but also all kinds of
string construction as a countermeasure to numerous/various kinds
buffer related vulnerabilities. lots of past posts on buffer related
vulnerabilities
https://www.garlic.com/~lynn/subintegrity.html#overflow
recent post mentioning
https://www.garlic.com/~lynn/2006p.html#43 Slow-Going For Next-Generation Threat-Scoring System
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: what's the difference between LF(Line Fee) and NL (New line) ? Newsgroups: bit.listserv.ibm-main,alt.folklore.computers Date: Tue, 05 Sep 2006 11:15:48 -0600Joe Pfeiffer writes:
in addition to cms being done at the science center
https://www.garlic.com/~lynn/subtopic.html#545tech
previous ref in this thread
https://www.garlic.com/~lynn/2006p.html#51 what's the difference between LF(Line Fee) and NL (New line) ?
gml was invented at the science center in 1969 and support added to
cms script ... recent cms script ref:
https://www.garlic.com/~lynn/2006p.html#27 What part of z/OS is the OS?
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: what's the difference between LF(Line Fee) and NL (New line) ? Newsgroups: bit.listserv.ibm-main,alt.folklore.computers Date: Wed, 06 Sep 2006 08:30:22 -0600Joe Pfeiffer writes:
ref:
https://www.garlic.com/~lynn/2006p.html#52 what's the difference between LF(Line Fee) and NL (New line) ?
are we talking about gml (precursor to sgml, html, xml and various
other markup languages)? :)
https://www.garlic.com/~lynn/submain.html#sgml
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Douglas Engelbart's HyperScope 1.0 Launched Newsgroups: alt.folklore.computers Date: Wed, 06 Sep 2006 08:40:16 -0600Douglas Engelbart's HyperScope 1.0 Launched
and
Douglas Engelbart's HyperScope 1.0 Launched
http://slashdot.org/articles/06/09/05/2319250.shtml
from above:
"HyperScope 1.0 is a new Web app based on Douglas Engelbart's 1968
NLS/Augment (oNLine System). Engelbart and team have been working on
Hyperscope since March of this year in a project funded by the
National Science Foundation."
... snip ...
NLS/Augment was one of the things at Tymshare ... at the time M/D bought it.
misc. post from earlier this year mentioning augemnt
https://www.garlic.com/~lynn/2006n.html#50 stacks: sorting
misc. posts from earlier this year mentioning Tymshare:
https://www.garlic.com/~lynn/2006b.html#39 another blast from the past
https://www.garlic.com/~lynn/2006h.html#9 It's official: "nuke" infected Windows PCs instead of fixing them
https://www.garlic.com/~lynn/2006h.html#15 Security
https://www.garlic.com/~lynn/2006k.html#29 PDP-1
https://www.garlic.com/~lynn/2006k.html#37 PDP-1
https://www.garlic.com/~lynn/2006k.html#39 PDP-1
https://www.garlic.com/~lynn/2006m.html#34 PDP-1
https://www.garlic.com/~lynn/2006n.html#3 Not Your Dad's Mainframe: Little Iron
https://www.garlic.com/~lynn/2006o.html#49 The Fate of VM - was: Re: Baby MVS???
https://www.garlic.com/~lynn/2006p.html#13 What part of z/OS is the OS?
From: Anne & Lynn Wheeler <lynn@garlic.com> Subject: Re: PowerPC or PARISC? Newsgroups: comp.arch Date: Wed, 06 Sep 2006 13:33:48 -0600Del Cecchi writes:
i triped across a redbook found by a search engine that discussed sql
server 2005 scaling on x3/hurricane ... mentioned both single shared
numa memory operation and partitioned operation (possibly using
memory for doing message passing?).
http://www.redbooks.ibm.com/redpapers/pdfs/redp4093.pdf
however i didn't find anything that went into next level detail (stuff like you would find in something like sci numa memory architecture description and how cache coherency actually operated)
one of the xeon talks at hotchips got into some scale-up cache consistency issues ... and there were some questions related to possible stalling/starvation deadlocks in the implementations ... however, you may have to pay the $55 for the cdrom.
the freebees
http://www.hotchips.org/hc18/presentations.htm
and the cdrom presentations (was well as the dvd videos):
http://www.hotchips.org/hc18/store.htm